GATE/NET Digital Logic Design Practice Test Set8
Q11➡ |
Which of the following statements is FALSE? |
| i ➥ Johnson counter is a synchronous counter |
| ii ➥ Ripple counter is an asynchronous counter. |
| iii ➥ Asynchronous counters are slower than synchronous counters. |
| iv ➥ A counter may count up or count down, but cannot count both up and down. |
Q12➡ |
How many address lines and data lines are required to provide a memory capacity of 16K x 16? |
| i ➥ 10,4 |
| ii ➥ 16,16 |
| iii ➥ 14,16 |
| iv ➥ 4,16 |
Q13➡ |
Which of the following is a sequential circuit? |
| i ➥ Multiplexer |
| ii ➥ Decoder |
| iii ➥ Counter |
| iv ➥ Full adder |
Q14➡ |
The characteristic equation of a T flip flop is given by : |
| i ➥ QN+1 = TQN |
| ii ➥ QN+1 = T+QN |
| iii ➥ QN+1 = TQN |
| iv ➥ QN+1=T’QN |
Q15➡ |
The characteristic equation of D flip-flop is : |
| i ➥ Q=1 |
| ii ➥ Q=0 |
| iii ➥ Q= D’ |
| iv ➥ Q=D |
11. iv
12..iii
13. iii
14.ii
15. iv
Ans 11- 4
Ans 12 – 3
Ans 13 – 3
Ans 14 – 2
Ans 15 – 3
Ans11-iv
Ans12-iii
Ans13-iii
Ans14-ii
Ans15-iv
11, IV
12, iii
13, iii
14, iii
15, IV
11-iv
13-iii
14- T’Qn + TQ’n
15-iv