Q51➡| NTA UGC NET January 2017 Paper-2 Consider the following assembly language instructions : mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H adc ah, 0 What is the value in ax register after execution of above instructions ?
Q52➡| NTA UGC NET January 2017 Paper-2 The contents of Register (BL) and Register (AL) of 8085 microprocessor are 49H and 3AH respectively. The contents of AL, the status of carry flag (CF) and sign flag (SF) after executing ‘SUB AL, BL’ assembly language instruction, are
Q59➡| NTA UGC NET July 2016 Paper-3 In________addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction.
Q64➡| NTA UGC NET July 2016 Paper-3 The_______addressing mode is similar to register indirect addressing mode, except that an offset is added to the contents of the register. The offset and register are specified in the instruction.
Q68➡| NTA UGC NET December 2015 Paper-3 A DMA controller transfers 32-bit words to memory using cycle stealing. The words are assembled from a device that transmits characters at a rate of 4800 characters per second. The CPU is fetching and executing instructions at an average rate of one million instructions per second. By how much will the CPU be slowed down because of the DMA transfer?
Q70➡ |NTA UGC NET December 2015 Paper III A dynamic RAM has refresh cycle of 32 times per msec. Each refresh operation requires 100 nsec and a memory cycle requires 250 nsec. What percentage of memory’s total operating time is required for refreshes?
Q71➡| NTA UGC NET June 2015 Paper-2 In the case of parallelization, Amdahl’s law states that if P is the proportion of a program that can be made parallel and (1 -P) is the proportion that cannot be parallelized, then the maximum speed-up that can be achieved by using N processors is:
Q72➡| NTA UGC NET June 2015 Paper-2 Consider a 32 – bit microprocessor, with a 16 – bit external data bus, driven by an 8 MHz input clock. Assume that this microprocessor has a bus cycle whose minimum duration equals four input clock cycles. What is the maximum data transfer rate for this microprocessor?
Q74➡| NTA UGC NET June 2015 Paper-3 The CPU of a system having 1 MIPS execution rate needs 4 machine cycles on an average for executing an instruction. The fifty percent of the cycles use memory bus. A memory read/ write employs one machine cycle. For execution of the programs, the system utilizes 90 percent of the CPU time. For block data transfer, an IO device is attached to the system while CPU executes the background programs continuously. What is the maximum IO data transfer rate if programmed IO data transfer technique is used?
Q76➡| NTA UGC NET December 2014 Paper-3 A hierarchical memory system that uses cache memory has cache access time of 50 nano seconds, main memory access time of 300 nanoseconds, 75% of memory requests are for read, hit ratio of 0.8 for read access and the write-through scheme is used. What will be the average access time of the system both for read and write requests ?
Q81➡| NTA UGC NET December 2014 Paper-3 How many characters per second (7 bits + 1 parity) can be transmitted over a 3200 bps line if the transfer is asynchronous ? (Assuming 1 start bit and 1 stop bit)