Computer System Architecture Subject Wise UGC NET Question Analysis

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Explanation:
It is given that,
hit ratio = 0.8 or 80% ,
memory access time = 150 ns,
TLB access time = 15ns,
Miss ratio = 1- hit ratio = 1 – 0.8 = 0.2

Effective memory access time
= hit ratio (memory access time + TLB access time) + miss ratio (2memory access time + TLB access time)
= 0.8(150 + 15) + 0.2* (2150 + 15)
= 0.8 165 + 0.2 * 315
= 132 + 63
= 195 ns

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Explanation:
Direct mapped cache:
In a direct-mapped cache structure, the cache is organized into multiple set with a single cache line per set. Based on the address of the memory block, it can only occupy a single cache line. The cache can be framed as a (n*1) column matrix.

Main memory offset In above,
Main memory size = 216 B
Block size = 8 B = 23 B , Block offset = 3
Cache line = 32 B = 25 B,  Cache line offset = 5 Tag bits = main memory offset – (line offset + Block offset)
= 16 – (5 + 3)
= 16 – 8 = 8

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Explanation:
Statement I: hardwired control unit can be optimized to produce fast modes of operations.
hardwired control unit can be uses a large number of registers and because of that it is costly.
hardwired control unit Instruction size in the Hardwired unit is fixed.
hardwired control unit has a small number of addressing modes.
Statement(I) is True
Statement II: Indirect addressing mode needs two memory references to fetch the operand.
In indirect addressing mode, instructions contain the address of an operand where operand is actually present. It requires two memory access to fetch the operand.
Example: The address part of an instruction contains 300. Now the control go at address 300 to find the address of an operand. The address of an operand in this example is 500. The operand found at loaction 500. Indirect Addreesing need two memory reference, one for to find address of an operand & another one for operand itself.
Statement(I) is True

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Explanation:
MIMD < SIMD < SISD

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Explanation:
Period = 100 ms = 100*10-3 = 10-1s
Frequency
= 1 / period
= 1 / 100*10-3
= (1 / 10-1) Hz
= (1 / 10-1 * 103) KHz
= 1 / 102 KHz
= 10-2 KHz

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Explanation:
Time required to execute 100 tasks without pipeline = 100* 30 = 3000 ns
Time required to execute 100 tasks with 4-stages pipeline
= Time taken by 1st task + Time taken by remaining 99 tasks
= 1 * 4 clock cycle + 99 * 1 clock cycle
= 4 * 10 + 99 * 10
= 40 + 990
= 1030 ns
Speedup
= Time required without pipeline / Time required with pipeline
= 3000 / 1030
= 2.91
Or
Speedup
= Time required without pipeline / Time required with pipeline
= n * Tn / (n + k – 1) Tp

where,
Tn = clock cycle without pipeline,
n = total number of tasks,
k = number of segment,
Tp = clock cycle with pipeline

Speedup
= n * Tn / (n + k – 1) Tp
= 100 * 30 / (100 + 4 – 1) * 10
= 3000 / 1030
= 2.91 ns

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Explanation:
A microinstruction format has microoperation field which is divided into 2 subfields F1 and F2.
Each having 15 distinct micro operations.
Bits required =log215 = 3 bits each

Condition field CD have four status bits.
Bits required = log2 4 = 2 bits

Branch field BR having four options used in conjunction with address field AD.
Bits required = log2 4 = 2 bits

The address space is of 128 memory words.
Bits required = log2 128 = 7 bits Micro instruction size
= F1 + F2 + CD + BR + ADR
= 3+3+2+2+7
= 17 bits

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Explanation:
It is given that ,

TLB access time = 20ns
Memory access time = 80ns
hit ratio = 80% (or 0.8)
miss ratio = 1 – 0.8 = 0.2(or 20%)

effective memory access
= hit ratio * (TLB access time + memory access time) + miss ratio * (TLB access time + memory access time)
= 0.8(20+80) + 0.2(20+280)
= 0.8 * 100 + 0.2*180
= 80 + 36
= 116 ns

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Answer: marks are given to all in this question by NTA

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