Q2➡| NET December 2022 Consider an unpipelined machine with 10nsec clock cycles which uses four cycles for ALU operations and branches where as five cycles for memory operation. Assume that the relative frequencies of these operations are : 40%, 20% and 40 %, respectively. Due to clock skew and setup pipeline let us consider that the machine adds one nsec overhead to the clock. How much speedup is observed in the instruction execution rate when a pipelined machine is considered?
i ➥ 2 times
ii ➥ 4 times
iii ➥ 6 times
iv ➥ 8 times
Best Explanation: Answer: (ii) Explanation: Upload Soon
Q3➡| NET December 2022 Which of the following is/are true for Dynamic RAM (DRAM) ? (A) It is slower than static RAM (SRAM) (B) Packing Density is Higher than Static RAM (SRAM) (C) It’s faster than Static RAM (SRAM) (D) It is requires data refreshing which of the correct answer from the options given below :
i ➥ A, B and D only
ii ➥ A, B and C only
iii ➥ C and D only
iv ➥ B and D only
Best Explanation: Answer: (i) Explanation: Upload Soon
Q4➡| NET December 2022 Which of the following statement is/are false? A : The processor has direct access to both primary and secondary memory B : Primary memory stores the active instructions and data for the program being executed on the process C : Secondary memory is used as a backup memory D : memory system is implemented on a single level memory Choose the correct answer from the options given below :
i ➥ A and B only
ii ➥ B and C only
iii ➥ A, B and C only
iv ➥ A and D only
Best Explanation: Answer: (iv) Explanation: Upload Soon
Q6➡| NET December 2022 The Correct sequence in fetch- executes cycle is …………. (A) Decode (B) Fetch (C) Execute Choose the correct answer from the following
i ➥ A-B-C
ii ➥ B-C-A
iii ➥ C-B-A
iv ➥ B-A-C
Best Explanation: Answer: (iv) Explanation: Upload Soon
Q7➡| NET June 2022 In a cache memory , if address has 9 bits in Tag field and 12 bits in index field, the size of main memory and cache memory would be respectively
i ➥ 2K, 4K
ii ➥ 1024K, 2K
iii ➥ 4K, 2048K
iv ➥ 2048K, 4K
Best Explanation: Answer: (iv) Explanation: Upload Soon
Q8➡| NET June 2022 Consider the following related to Fourth Generation Technique (4GT): (A) It controls efforts (B) It controls resources (C) It controls cost of development. Choose the correct answer from the options given below:
i ➥ (A) and (B) only
ii ➥ (B) and (C) only
iii ➥ (C) and (A) only
iv ➥ All (A), (B) and (C)
Best Explanation: Answer: (iv) Explanation: Upload Soon
Q9➡| NET June 2022 Consider a memory system having address spaced at a distance of m , T = Bank cycle time and n number of banks , then the average data access time per word access in synchronous organization is
i ➥
ii ➥
iii ➥
iv ➥
Best Explanation: Answer: (i) Explanation: Upload Soon
Q10➡| NET June 2022 The total storage capacity of a floppy disk having 80 tracks and storing 128 bytes/sector is 163,840 bytes . How many sectors does this disk have ?
i ➥ 27
ii ➥ 2048
iii ➥ 4K
iv ➥ 16
Best Explanation: Answer: (iv) Explanation: Upload Soon
Q12➡| NET June 2022 A 4-stage pipeline has the delay as 150, 120, 160 and 140 ns respectively . registers that are used between the stage have delay of 5 ns. Assuming constant locking rate , the total time required to process 1000 data items on this pipeline is
i ➥ 160.5 ns
ii ➥ 165.5 ns
iii ➥ 120.5 ns
iv ➥ 590.5 ns
Best Explanation: Answer: (ii) Explanation: Upload Soon
Q13➡| NET June 2022 A magnetic tape drive has transport speed of 200 inches per second and a recording density of 1600 bytes per inch. The time required to write 600000 bytes of date grouped in 100 charaters record with a blocking factor 10 is
i ➥ 2.0625 sec
ii ➥ 2.6251 sec
iii ➥ 2.0062 sec
iv ➥ 2.6150 sec
Best Explanation: Answer: (i) Explanation: Upload Soon
Q1➡| NET June 2021 Given below are three statements related to interrupt handling mechanism A. Interrupt handler routine is not stored at a fixed address in the memory. B. CPU hardware has a dedicated wire called the interrupt request line used for handling interrupts C. Interrupt vector contains the memory addresses for speciaized interrupt handlers. In the context of above statements, choose the correct answer from the options given below: Options:-
Q2➡| NET June 2021 Which of the following statement is true? A. Control memory is part of the hardwired control unit. B. Program control instructions are used to alter the sequential flow of the program. C. The register indirect addressing mode for accessing memory operand is similar to displacement addressing mode. D. CPU utilization is not affected by the introduction of Interrupts.
Q4➡| NET June 2021 Given below are two statements Statement I: CISC computers have a large of number of addressing modes. Statement II: In RISC machines memory access is limited to load and store instructions. In light of the above statements, choose the correct answer from the options given below
i ➥Both Statement I and Statement II are false
ii ➥ Both Statement I and Statement II are true
iii ➥Statement I is false but Statement II is true
Q5➡ | NET June 2021 The cache coherence problem can be solved A. by having multiport memory B. allow only nonshared data to be stored in cache C. using a snoopy cache controller D. using memory interleaving Choose the correct answer from the options given below:
Q6➡| NET June 2021 Arrange the following in the increasing order of complexity. A. I/O Module B. I/O processor C. I/O Channel D. DMA Choose the correct answer from the options given below Options:-
Q7➡|UGC NET November 2020 Consider a single-level page table system, with the page table stored in the memory. If the hit rate to TLB is 80%, and it takes 15 nanoseconds to search the TLB, and 150 nanoseconds to access the main memory, then what is the effective memory access time, in nanoseconds?
i➥ 185
ii ➥ 195
iii ➥205
iv ➥ 175
Show Answer With Best Explanation
Answer: II Explanation: It is given that, hit ratio = 0.8 or 80% , memory access time = 150 ns, TLB access time = 15ns, Miss ratio = 1- hit ratio = 1 – 0.8 = 0.2
Effective memory access time = hit ratio (memory access time + TLB access time) + miss ratio (2memory access time + TLB access time) = 0.8(150 + 15) + 0.2* (2150 + 15) = 0.8 165 + 0.2 * 315 = 132 + 63 = 195 ns
Q8➡|UGC NET November 2020 A non-pipeline system takes 50ns to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10ns. Determine approximately the speedup ratio of the pipeline for 500 tasks.
i➥ 6
ii ➥ 4.95
iii ➥5.7
iv ➥ 5.5
Answer: II Explanation: Given, Total Stage (k) = 6 Time taken by non-pipeline system(Tnp) = 50ns Time taken by pipeline system(Tp) = 10ns
Formula, Time required to execute n tasks without pipeline = n*Tnp Time required to execute n tasks with k-stages pipeline = = (k+n-1)*Tp
Let’s solve, Time required to execute 500 tasks without pipeline = n*Tnp = 500* 50 = 25000 ns Time required to execute 500 tasks with 6-stages pipeline = Time taken by 1st task + Time taken by remaining 499 tasks = 1 x 6 clock cycles + 499 x 1 clock cycle = 6 clock time + 499 clock time = 6* 10 + 499* 10 = 60 + 4990 = 5050ns
or
Time required to execute 500 tasks with 6-stages pipeline = (k+n-1)*Tp =(6+500-1)*10 = 505*10 = 5050ns
Q9➡| UGC NET November 2020 Consider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine. How many bits will be there in Tag, line and word field of format of main memory addresses?
i➥ 8,5,3
ii ➥ 8,6,2
iii ➥7,5,4
iv ➥ 7,6,3
Show Answer With Best Explanation
Answer: I Explanation: Direct mapped cache: In a direct-mapped cache structure, the cache is organized into multiple set with a single cache line per set. Based on the address of the memory block, it can only occupy a single cache line. The cache can be framed as a (n*1) column matrix.
Main memory offset In above, Main memory size = 216 B Block size = 8 B = 23 B , Block offset = 3 Cache line = 32 B = 25 B, Cache line offset = 5
Q10➡| UGC NET November 2020 Given below are two statements: Statement I: hardwired control unit can be optimized to produce fast mode of operation. Statement II: Indirect addressing mode needs two memory references to fetch the operand.
In the light of the above statements, choose the correct answers from the options given below
i➥ Both Statement I and Statement II are true
ii ➥ Both Statement I and Statement II are false
iii ➥Statement I is correct but Statement II is false
iv ➥ Statement I is incorrect but Statement II is true
Show Answer With Best Explanation
Answer: I Explanation: Statement I:hardwired control unit can be optimized to produce fast modes of operations. hardwired control unit can be uses a large number of registers and because of that it is costly. hardwired control unit Instruction size in the Hardwired unit is fixed. hardwired control unit has a small number of addressing modes. Statement(I) is True Statement II:Indirect addressing mode needs two memory references to fetch the operand. In indirect addressing mode, instructions contain the address of an operand where operand is actually present. It requires two memory access to fetch the operand. Example: LOAD R1, @300 The address part of an instruction contains 300. Now the control go at address 300 to find the address of an operand. The address of an operand in this example is 500. The operand found at loaction 500. Indirect Addreesing need two memory reference, one for to find address of an operand & another one for operand itself. Statement(I) is True
Q12➡| UGC NET November 2020 Arrange the following types of machine in descending order of complexity. (A) SISD (B) MIMD (C) SIMD Choose the correct answer from the options given below:
Q13➡| UGC NET November 2020 Which of the following statements with respect to K-segment pipelining are true? A) Maximum speedup that a pipeline can provide is k theoretically. B) It is impossible to achieve maximum speedup k in the k-segment pipeline. C) All segments in the pipeline take the same time in computation.
Choose the correct answer from the options given below:
Q14➡|UGC NET November 2020 The following program is stored in the memory unit of the basic computer. What is the content of the accumulator after the execution of the program? (All location numbers listed below are in hexadecimal)
Q16➡|NTA UGC NET November 2020 Comprehension:Question 16-20 concerns a disk with a sector size of 512 bytes, 2000 tracks per surface.50 sectors per track, five double-sided platters, and average seek time of 10 milliseconds.
Q16: If one track of data can be transferred per revolution, then what is the data transfer rate?
Q17➡|NTA UGC NET November 2020 Comprehension:Question 16-20 concerns a disk with a sector size of 512 bytes, 2000 tracks per surface.50 sectors per track, five double-sided platters, and average seek time of 10 milliseconds.
Q17: Given below are two statements: Statement I: The disk has a total number of 2000 cylinders. Statement II: 51200 bytes is not a valid block size for the disk.
In the light of the above statements, choose the correct answer from the options given below:
i➥ Both Statement I and Statement II are true
ii ➥ Both Statement I and Statement II are false
iii ➥Statement I is correct but Statement II is false
iv ➥ Statement I is incorrect but Statement II is true
Q18➡|NTA UGC NET November 2020 Comprehension:Question 16-20 concerns a disk with a sector size of 512 bytes, 2000 tracks per surface.50 sectors per track, five double-sided platters, and average seek time of 10 milliseconds.
Q18: If T is the capacity of a track in bytes, and S is the capacity of each surface in bytes, then (T,S) = __________.
Q19➡|NTA UGC NET November 2020 Comprehension:Question 16-20 concerns a disk with a sector size of 512 bytes, 2000 tracks per surface.50 sectors per track, five double-sided platters, and average seek time of 10 milliseconds.
Q20➡|UGC NET November 2020 Comprehension:Question 16-20 concerns a disk with a sector size of 512 bytes, 2000 tracks per surface.50 sectors per track, five double-sided platters, and average seek time of 10 milliseconds.
Q20: If the disk platters rotate at 5400 rpm (revolutions per minute), then approximately what is the maximum rotational delay?
Q21➡| UGC NET December 2019 A Non-pipelined system takes 30ns to process a task. The same task can be processed in a four-segment pipeline with a clock cycle of 10ns. Determine the speed up of the pipeline for 100 tasks
i➥ 3
ii ➥ 4
iii ➥3.91
iv ➥ 2.91
Show Answer With Best Explanation
Answer: IV Explanation: Time required to execute 100 tasks without pipeline = 100* 30 = 3000 ns Time required to execute 100 tasks with 4-stages pipeline = Time taken by 1st task + Time taken by remaining 99 tasks = 1 * 4 clock cycle + 99 * 1 clock cycle = 4 * 10 + 99 * 10 = 40 + 990 = 1030 ns Speedup = Time required without pipeline / Time required with pipeline = 3000 / 1030 = 2.91 Or Speedup = Time required without pipeline / Time required with pipeline = n * Tn / (n + k – 1) Tp
where, Tn = clock cycle without pipeline, n = total number of tasks, k = number of segment, Tp = clock cycle with pipeline
Q22➡|UGC NET December 2019 The reduced Instruction Set Computer (RISC) characteristics are: (a) Single cycle instruction execution (b) Variable length instruction formats (c) Instructions that manipulates operands in memory (d) Efficient instruction pipeline
Choose the correct characteristics from the options given below:
Q23➡| UGC NET December 2019 A micro instruction format has micro operation field which is divided into 2 sub fields F1 and F2. Each having 15 distinct micro operations condition field CD for four status bits. Branch field BR having four options used in conjunction with address field AD. The address space is of 128 memory words. The size of micro instruction is
i➥ 19
ii ➥ 18
iii ➥17
iv ➥ 20
Show Answer With Best Explanation
Answer: III Explanation: A microinstruction format has microoperation field which is divided into 2 subfields F1 and F2. Each having 15 distinct micro operations. Bits required =log215 = 3 bits each
Condition field CD have four status bits. Bits required = log2 4 = 2 bits
Branch field BR having four options used in conjunction with address field AD. Bits required = log2 4 = 2 bits
The address space is of 128 memory words. Bits required = log2 128 = 7 bits Micro instruction size = F1 + F2 + CD + BR + ADR = 3+3+2+2+7 = 17 bits
Q24➡| UGC NET December 2019 Consider a paging system where translation lookaside buffer (TLB) a special type of associative memory is used with hit ratio of 80%. Assume that memory reference takes 80 nanoseconds and reference time to TLB is 20 nanoseconds. What will be the effective memory access time given 80% hit ratio?
i➥ 110 nanoseconds
ii ➥ 116 nanoseconds
iii ➥200 nanoseconds
iv ➥ 100 nanoseconds
Show Answer With Best Explanation
Answer: II Explanation: It is given that ,
TLB access time = 20ns Memory access time = 80ns hit ratio = 80% (or 0.8) miss ratio = 1 – 0.8 = 0.2(or 20%)
effective memory access = hit ratio * (TLB access time + memory access time) + miss ratio * (TLB access time + memory access time) = 0.8(20+80) + 0.2(20+280) = 0.8 * 100 + 0.2*180 = 80 + 36 = 116 ns
Q25➡| UGC NET December 2019 A computer uses a memory unit of 512 K words of 32 bits each. A binary instruction code is stored in one word of the memory. The instruction has four parts: an addressing mode field to specify one of the two-addressing mode (direct and indirect), an operation code, a register code part to specify one of the 256 registers and an address part. How many bits are there in addressing mode part, opcode part, register code part and the address part?
Q27➡| UGC NET December 2019 An instruction is stored at location 500 with it address field at location 501. The address field has the value 400. A processor register R1 contains the number 200. Match the addressing mode (List-I) given below with effective address (List-II) for the given instruction: Choose the correct option from those given below:
Q29➡| UGC NET December 2019 The following program is stored in the memory unit of the basic computer. Give the content of accumulator register in hexadecimal after the execution of the program.
Q31➡| UGC NET June 2019 Suppose that the register A and register K have the bit configuration. Only the three leftmost bits of A are compared with memory words because K has 1’s in these positions. Because of its organization, this type of memory is uniquely suited to parallel searches by data association. This type of memory is known as
Q34➡| UGC NET June 2019 Suppose that a computer program takes 100 seconds of execution time on a computer with multiplication operation responsible for 80 seconds of this time. How much do you have to improve the speed of multiplication operation if you are asked to execute this program four times faster.
Q35➡| UGC NET December 2018 Consider a disk pack with 32 surfaces, 64 tracks and 512 sectors per pack. 256 bytes of data are stored in a bit serial manner in a sector. The number of bits required to specify a particular sector in the disk is.
Q37➡| UGC NET December 2018 Consider the following x86 – assembly language instructions : MOV AL, 153 NEG AL The contents of the destination register AL (in 8-bit binary notation), the status of Carry Flag(CF) and Sign Flag(SF) after the execution of above instructions, are
Q38➡| UGC NET December 2018 Consider the following statements : (i) Auto increment addressing mode is useful in creating self-relocating code. (ii) If auto addressing mode is included in an instruction set architecture, then an additional ALU is required for effective address calculation. (iii) In auto increment addressing mode, the amount of increment depends on the size of the data item accessed. Which of the above statements is/are true ?
Q39➡| UGC NET June 2018 Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O ?
i ➥ I/O protection is ensured by operating system routines.
ii ➥ I/O protection is ensured by a hardware trap.
iii ➥ I/O protection is ensured during system configuration.
Q45➡| UGC NET November 2017 Paper-3 Which of the following addressing mode is best suited to access elements of an array of contiguous memory locations ?
Q47➡| UGC NET November 2017 Paper-3 A micro-instruction format has micro-ops field which is divided into three sub-fields F1, F2, F3 each having seven distinct micro-operations, condition field CD for four status bits, branch field BR having four options used in conjunction with address field ADF. The address space is of 128 memory locations. The size of micro-instruction is:
Q48➡| UGC NET November 2017 Paper-3 Consider the following assembly program fragment : stc mov al, 11010110b mov cl, 2 rcl al, 3 rol al, 4 shr al, cl mul cl The contents of the destination register ax (in hexadecimal) and the status of Carry Flag (CF) after the execution of above instructions, are:
Q50➡| UGC NET January 2017 Paper-3 The general configuration of the micro-programmed control unit is given below: What are blocks B and C in the diagram respectively?
