Digital Logic Design NTA NET Questions


Q.1➡ | UGC NET DEC 2023
Which of the following circuit is used to store one bit of data ?
i ➥ Encoder
ii ➥ Decoder
iii ➥ Flip-Flop
iv ➥ Register
Best Explanation:
Answer: (III)
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Q2➡ | UGC NET DEC 2023
Identify the code sequence :
1010
1011
1001
1000
i ➥ BCD
ii ➥ Excess-3
iii ➥ Gray
iv ➥ Excess-3 gray
Best Explanation:
Answer: (III)
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Q.3➡ | UGC NET JUNE 2023
Find the sum of all four digit numbers formed using the digits 1,2,4 and 6.
i ➥ 86,658
ii ➥ 88,8858
iii ➥ 91,958
iv ➥ 93,358
Best Explanation:
Answer: I
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Q.4➡ | UGC NET JUNE 2023
Let denote XOR operation. Let 1 and 0 denote the binary constants and F is the Boolean expression over two variables P and Q
F(P,Q) = ((1⊕ P) ⊕(P⊕Q)) ⊕ ((P ⊕ Q) ⊕ (Q⊕0))
Which of the following is equivalent expression to F?
i ➥ P⊕Q
ii ➥ P+Q
iii ➥ (P+Q)’
iv ➥ (P⊕Q)’
Best Explanation:
Answer: IV
Explanation: (Repeated Question Please Remember this on
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Q.5➡ | UGC NET JUNE 2023
What is the (4+4) fit binary fixed point equivalent of -(3.72)10 ?
i ➥ 0011.1100
ii ➥ 0011.1010
iii ➥ 1100.0100
iv ➥ 0011.1011
Best Explanation:
Answer: III
Explanation:
Integer part:
• The integer part of -3 is 33 in binary, which is 00110011 in 4 bits.

Fractional part:
• Convert the fractional part 0.720.72 to binary:
• 0.72×2=1.440.72×2=1.44 (First bit: 1)
• 0.44×2=0.880.44×2=0.88 (Next bit: 0)
• 0.88×2=1.760.88×2=1.76 (Next bit: 1)
Continuing this process:
• 0.76×2=1.520.76×2=1.52 (Next bit: 1)
• 0.52×2=1.040.52×2=1.04 (Next bit: 1)
• 0.04×2=0.080.04×2=0.08 (Next bit: 0)
• 0.08×2=0.160.08×2=0.16 (Next bit: 0)
• The binary representation of 0.720.72 is 1011010010110100.

Combine the binary representations:
• Combine the integer and fractional parts with the binary point:
• 0011.101101000011.10110100
Adjust to (4+4) fit binary fixed-point:
• The total number of bits is 8 (4 bits for the integer part and 4 bits for the fractional part).
• So, we need to truncate or round to fit into the (4+4) format. In this case, we truncate the extra bits.
• The result is 1100.01001100.0100.
Therefore, the correct answer is:
iii ➥ 1100.0100
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Q.6➡ | NET December 2022
The memory size for n address lines and m data lines is given by
i ➥ 2m×n
ii ➥ m×n2
iii ➥ 2n×m
iv ➥ n×m2
Best Explanation:
Answer: (iii)
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Q.7➡ | NET December 2022
Simplify the following using K-map
F(A, B, C, D) = Σ(0, 2, 5, 7, 8, 10, 13, 15)
i ➥ BD + B’D’
ii ➥ AC + A’C’
iii ➥ BC + B’C’
iv ➥ AD + A’D’
Best Explanation:
Answer: (i)
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Q.8➡ | NET June 2022
Consider a logic gate circuit, with 8 input lines (D0, D1………..D7) and 3 input Lines (A0, A1, A2) specified by following operations
A2=D4+D5+D6+D7
A1=D2+D3+D6+D7
A0=D1+D3+D5+D0
Where + indicates logical OR operation. This circuit is
i ➥ 3×8 multiplexer
ii ➥ Decimal to BCD Converter
iii ➥ Octal to Binary encoder
iv ➥ Priority encoder
Best Explanation:
Answer: (iv)
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Q.9➡ | NET June 2022
The number of gate inputs, required to realize expression ABC+AB̅CD+E Fbar+AD is
i ➥ 12
ii ➥ 13
iii ➥ 14
iv ➥ 15
Best Explanation:
Answer: (iv)
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Question 10➡ | NTA UGC NET June 2021
The Octal equivalent of hexadecimal (D.C)16 is:
i ➥ (15.3)8
ii ➥ (15.6)8
iii ➥ (61.3)8
iv ➥ (61.6)8

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Answer: II
Explanation:
Given,
(D.C)16
Calculation,
To obtain octal equivalent for a given number , first convert into base 2 representation and then make a group of 3 bits.
why 3 bits? Because octal representation have base 8 and log28 = 3bits.
(D)16 = (13)10 = (1101)2
(C)16 = (12)10 = (1100)2
(D.C)16 = (1101.1100)2
make a pair of 3 bits
(D.C)16 = (001 101.110 000)2 = (15.60)8 = (15.6)8
So, Option(II) is correct.

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Question .11➡ | NTA UGC NET June 2021
Match List I with List II

Choose the correct answer from the options given below:
i ➥ A – I, B -III , C – IV, D – II
ii ➥ A – III, B -I , C – II, D – IV
iii ➥ A – III, B -I , C – IV, D – II
iv ➥ A – III, B -IV , C – I, D – II

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Answer: III
Explanation:
Some Boolean algebra laws:
i) Identity Law
x + 0 = x , x .1 = x
ii) Absorption Law
x + xy = x , x.(x + y) = x
iii) Idempotent Law
x + x = x , x . x = x
iv) Domination Law
x + 1 = 1 , x . 0 = 0
v) Commutative Law
x + y = y + x , x . y = y . x
vi) Associative Law
x + (y + z) = (x + y) + z , x .(y . z) = (x . y). z
vii) Distributive Law
x.(y + z) = x.y + x.z , x + (y.z) = (x + y).(x + z)
viii) Complementation Law
x + x’ = 1 , x . x’ = 0
ix) DeMorgan’s Law
(x . y)’ = x’ + y’ , (x + y)’ = x’ . y’

So, Option(III) is correct.

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Question. 12➡ | NTA UGC NET June 2021
Match List I with List II

Choose the correct answer from the options given below:Match List I with List II
i ➥ A – I, B – II, C – III, D – IV
ii ➥ A – I, B – III, C – II, D – IV
iii ➥ A – II, B – I, C – IV, D – III
iv ➥ A – IV, B – II, C – III, D – I

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Answer: III
Explanation:
ODD Function: X-OR is an ODD Function Because it gives High output for Odd number of High inputs.
Le us check for two input A and B
Logical equation of X-OR gate.
Y = AMatch List I with List IIB = AB’ + A’B
Match List I with List II List List II A.ODD function I. NAND gate B. universal gate II. XOR gate C. 2421 code III. Amplification D. Buffer IV. Self complementing
Universal Gate: The NAND Gate and NOR Gate are said to be Universal Gate because any Logic circuit can be implemented with it.
Self Complementing Code: In Self Complementing code, the code of a digit and the code of 9’s complement of the digit are 1’s complement to each other.
2421 code
let’s take decimal number 2,
9’s complement of the digit 2 = 7
the 2421 code of a digit 2 = 0010 ………….Code(1)
the 2421 code of a digit 7 = 1101 ………….Code(2)
Code (1) and code(2) are 1’s complement to each other. That’s why 2421 code is self complement code.
Buffer: Amplification
So, Option(III) is correct.

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Question .13➡ | NTA UGC NET June 2021
The characteristics of the combinational circuits are:
A. Output at any time is function of inputs at that time
B. Contains memory elements
C. Do not have feedback paths
D. Clock is used to trigger the circuits to obtain outputs

Choose the correct answer from the options given below:
i ➥ A and B only
ii ➥ A and C only
iii ➥ B and C only
iv ➥ B and D only

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Answer: II
Explanation:
Combinational Circuits
• Combinational circuits are defined as time independent circuits which do not depends upon previous inputs to generate any output.
• Output depends upon only present input.
• As combinational circuit don’t have clock, they don’t require triggering.

The characteristics of the combinational circuits are: A. Output at any time is function of inputs at that time B. Contains memory elements C. Do not have feedback paths D. Clock is used to trigger the circuits to obtain outputs
A. Output at any time is function of inputs at that time. (True)
Outputs depend on present inputs only.
B. Contains memory elements. (False)
• Combinational Circuits does not have any memory elements because it depends on present inputs only.
C. Do not have feedback paths. (True)
D. Clock is used to trigger the circuits to obtain outputs. (False)
So, Option(II) is correct.

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Question .14➡ | NTA UGC NET June 2021
A digital computer has a common bus system for 8 registers 16 bits each. How many multiplexers are required to implement common bus? What size of multiplexers is required?
i ➥ 16, 16×1
ii ➥ 16, 8×1
iii ➥ 8, 16×1
iv ➥ 8, 8×1

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Answer: II
Explanation:
Given,
Number of registers = 8
Number of bits in each register = 16bits
Formula,
Number of multiplexer in the bus = number of bits in each register
Size of multiplexer : number of register X 1
Calculation,
Number of multiplexer in the bus:
Number of Multiplexer = number of bits in each register
Here, number of bits in each register = 16
Therefore, Number of register = 16
Size of multiplexer:
Size of multiplexer : number of register X 1
Here, number of register = 8
Therefore, Size of multiplexer = 8×1
So, Option(II) is correct.

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Question .15➡ | NTA UGC NET November 2020
Simplified expression/s for following Boolean function
F(A,B,C,D)=Σ(0,1,2,3,6,12,13,14,15) is/are
A) A’B’+AB+A’C’D’
B) A’B’+AB+A’CD’
C) A’B’+AB+BC’D’
D) A’B’+AB+BCD’

Choose the correct answer from the options given below:
i ➥ (A) only
ii ➥ (B) only
iii ➥ (A) and (B) only
iv ➥ (B) and (D) only

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Answer: IV
Explanation:
Two K-maps can be constructed from given Boolean Function:
F(A,B,C,D)=Σ(0,1,2,3,6,12,13,14,15)

Simplified expression/s for following Boolean function F(A,B,C,D)=Σ(0,1,2,3,6,12,13,14,15) is/are A) A'B'+AB+A'C'D' B) A'B'+AB+A'CD' C) A'B'+AB+BC'D' D) A'B'+AB+BCD' Choose the correct answer from the options given below: A) (A) only B) (B) only C) (A) and (B) only D) (B) and (D) only
Simplified expression/s for following Boolean function F(A,B,C,D)=Σ(0,1,2,3,6,12,13,14,15) is/are A) A'B'+AB+A'C'D' B) A'B'+AB+A'CD' C) A'B'+AB+BC'D' D) A'B'+AB+BCD' Choose the correct answer from the options given below: A) (A) only B) (B) only C) (A) and (B) only D) (B) and (D) only
Boolean Expression of K-maps are: (A’B’ + AB + A’CD’) and (A’B’ + AB + BCD’)
So, Option(IV) is correct.

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Question .16➡ | NTA UGC NET November 2020
What kind of clauses are available in conjunctive normal form?
i ➥ Disjunction of literals
ii ➥ Disjunction of variables
iii ➥ Conjunction of literals
iv ➥ Conjunction of variables

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Answer: I
Explanation:
Conjunctive normal form(CNF) or clausal normal form is a conjunction of one or more than one clauses, where a clause is a disjunction of literals; or it is a product of sums or an AND of ORs.
These are in conjunctive normal form:
(A + B’ + C’) . (D’ + E + F)
(A + B ) . (C)
(A + B )
(A)

Confusing Point: Literals vs variables
Suppose, we have a function F(A,B)
The variables of function are: A, B
The literals of function are: A, A’, B, B’ (a literal is a variable either in complemented form or uncomplemented form)

So, Option(I) is correct.

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Question .17➡ | NTA UGC NET November 2020
Consider a code with only four valid code words: 0000000000, 0000011111, 1111100000, and 1111111111. This code has distance 5. If the code word arrived is 0000000111 then the original code word must be _______.
i ➥ 0000011111
ii ➥ 0000000000
iii ➥ 1111100000
iv ➥ 1111111111

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Answer: I
Explanation:
Given,
Hamming Distance =5
Formula,
For error correction, The hamming distance between any two codeword is 2t+1, where t is error correcting bits.
Calculation,
=> 2t+1 = 5
=> t =2 bits
Now, let’s explore each option and see which codeword have hamming distance 2.
Hamming distance is number of 1’s in X-OR of two code.
Option(I):
Consider a code with only four valid code words: 0000000000, 0000011111, 1111100000, and 1111111111. This code has distance 5. If the code word arrived is 0000000111 then the original code word must be _______.
Hamming distance = 2
Option(II):
Consider a code with only four valid code words: 0000000000, 0000011111, 1111100000, and 1111111111. This code has distance 5. If the code word arrived is 0000000111 then the original code word must be _______.
Hamming distance = 3
Option(III):
Consider a code with only four valid code words: 0000000000, 0000011111, 1111100000, and 1111111111. This code has distance 5. If the code word arrived is 0000000111 then the original code word must be _______.
Hamming distance = 8
Option(IV):
Consider a code with only four valid code words: 0000000000, 0000011111, 1111100000, and 1111111111. This code has distance 5. If the code word arrived is 0000000111 then the original code word must be _______.
Hamming distance = 7
Only option(I) have hamming distance 2.
So, Option(I) is correct.

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Question .18➡ | NTA UGC NET December 2019
Which of the following binary codes for decimal digits are self complementing?
(a) 8421 code
(b) 2421 code
(c) excess-3 code
(d) excess-3 gray code

Choose the correct option:
i ➥ (a) and (b)
ii ➥ (b) and (c)
iii ➥ (c) and (d)
iv ➥ (d) and (a)

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Answer: II
Explanation:
In Self Complementing code, The code of a digit and the code of 9’s complement of the digit are 1’s complement to each other.

Let’s take each one,
(a) 8421 code
let’s take decimal number 2,
9’s complement of the digit 2 = 7
the 8421 code of a digit 2 = 0010 ………….Code(1)
the 8421 code of a digit 7 = 0111 ………….Code(2)
Code(1) and code(2) are not 1’s complement to each other. That’s why 8421 code is not self complement code.

(b) 2421 code
let’s take decimal number 2,
9’s complement of the digit 2 = 7
the 2421 code of a digit 2 = 0010 ………….Code(1)
the 2421 code of a digit 7 = 1101 ………….Code(2)
Code (1) and code(2) are 1’s complement to each other. That’s why 2421 code is self complement code.

(c) excess-3 code
let’s take decimal number 2,
9’s complement of the digit 2 = 7
the excess-3 code of a digit 2 = 0101 ………….Code(1)
the excess-3 code of a digit 7 = 1010 ………….Code(2)
Code (1) and code(2) are 1’s complement to each other. That’s why excess-3 code is self complement code.

(d) excess-3 gray code
let’s take decimal number 2,
9’s complement of the digit 2 = 7
the excess-3 gray code of a digit 2 = 0111 ………….Code(1)
the excess-3 gray code of a digit 7 = 1111 ………….Code(2)
Code (1) and code(2) are not 1’s complement to each other. That’s why excess-3 code is not self complement code.
So, Option(II) is correct.

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Question .19➡ | NTA UGC NET December 2019
The Boolean AB+AB’+A’C+AC is unaffected by the value of the Boolean variable ___________.
i ➥ A
ii ➥ B
iii ➥ C
iv ➥ A, B & C

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Answer: II
Explanation:
=> AB+AB’+A’C+AC
=> A.(B+B’) + (A’+A).C
=> A.1 + 1.C
=> A + C
The Boolean AB+AB’+A’C+AC is unaffected by the value of the Boolean variable B.
So, Option(II) is correct.

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Question .20➡ | NTA UGC NET December 2019
Given following equation:
(142)b + (112)b-2 = (75)8
Find base b.
i ➥ 3
ii ➥ 6
iii ➥ 7
iv ➥ 5

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Answer: IV
Explanation:
(142)b + (112)b-2 = (75)8
convert into base 10
=> ( 1*b2 + 4*b1 + 2*b0 ) + ( 1*(b-2)2 + 1*(b-2)1 + 2*(b-2)0 ) = 7*81 + 5*80
=> ( b2 + 4b +2 ) + ( b2 + 4 -3b) = 61
=> 2b2 + b – 55 = 0
Formula,
if an equation is ax2 + bx +c =0
Given following equation: (142)b + (112)b-2 = (75)8 Find base b.
Given following equation: (142)b + (112)b-2 = (75)8 Find base b.
Given following equation: (142)b + (112)b-2 = (75)8 Find base b.
b = (-1+21)/4, (-1-21)/4
b = 5, -5.5
Base can’t be negative number.
So, Option(IV) is correct.

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Question .21➡ | NTA UGC NET June 2019
How many different Boolean functions of degree n are there?
i ➥ How many different Boolean functions of degree n are there? A)	22n    B)	(22)2 C)	22n-1 D)	2n
ii ➥ (22)2
iii ➥ 22n-1
iv ➥ How many different Boolean functions of degree n are there? A)	22n    B)	(22)2 C)	22n-1 D)	2n

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Answer: I
Explanation:
Total number of input sequence with n variable = 2n
Each input sequence have boolean value i.e 0 or 1.
How many different Boolean functions of degree n are there?
How many different Boolean functions of degree n are there?
Therefore, Total Boolean functions of degree n = How many different Boolean functions of degree n are there?
So, Option(I) is correct.

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Question .22➡ | NTA UGC NET June 2019
Consider the equation (146)b + (313)b-2 = (246)8 . Which of the following is the value of b?
i ➥ 8
ii ➥ 7
iii ➥ 10
iv ➥ 16

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Answer: II
Explanation:
(146)b + (313)b-2 = (246)8
convert into base 10
=> ( 1*b2 + 4*b1 + 6*b0 ) + ( 3*(b-2)2 + 1*(b-2)1 + 3*(b-2)0 ) = 2*82 + 4*81 + 6*80
=> ( b2 + 4b +6 ) + ( 3b2 + 13 -11b) = 166
=> 4b2 – 7b – 147 = 0
Formula,
if an equation is ax2 + bx +c =0
Given following equation: (142)b + (112)b-2 = (75)8 Find base b.
Consider the equation (146)b + (313)b-2 = (246)8 . Which of the following is the value of b?
Consider the equation (146)b + (313)b-2 = (246)8 . Which of the following is the value of b?
Consider the equation (146)b + (313)b-2 = (246)8 . Which of the following is the value of b?
b = (7+49)/8, (7-49)/8
b = 7, -6
Base can’t be negative number.
So, Option(IV) is correct.

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Question .23➡ | NTA UGC NET June 2019
How many address lines and data lines are required to provide a memory capacity of 16K x 16?
i ➥ 10,4
ii ➥ 16,16
iii ➥ 14,16
iv ➥ 4,16

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Answer: III
Explanation:
ROM memory size = 2m x n
where, m is address lines and n is data line.
Given,
ROM memory size = 16K x 16 = 214 x 16
Address line = 14
Data line = 16
So, Option(III) is correct.

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Question .24➡ | NTA UGC NET June 2019
Suppose that the register A and register K have the bit configuration. Only the three leftmost bits of A are compared with memory words because K has 1’s in these positions. Because of its organization, this type of memory is uniquely suited to parallel searches by data association. This type of memory is known as
i ➥ RAM
ii ➥ ROM
iii ➥ Content addressable memory
iv ➥ Secondary memory

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Answer: III
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Question .25➡ | NTA UGC NET June 2019
What will be the number of states when a MOD-2 counter is followed by a MOD-5 counter?
i ➥ 5
ii ➥ 10
iii ➥ 15
iv ➥ 20

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Answer: II
Explanation:
MOD-2 coumter followed by MOD-5 counter, it denotes cascading of two counters. Therefore,
equivalent counter = MOD (2 x 5) counter = MOD 10 counter.

Hence, the number of states when a MOD-2 counter is followed by a MOD-5 counter is 10.

MOD-10 counter is also called as BCD counter or Decade counter.
So, Option(II) is correct.

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Question .26➡ | NTA UGC NET June 2019
How many bit strings of length ten either start with a 1 bit or end with two bits 00?
i ➥ 320
ii ➥ 480
iii ➥ 640
iv ➥ 768

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Answer: III
Explanation:
Formula,
|AՍB| = A + B – |AՈB|
where,
A = number of bit strings of length ten start with 1
B = number of bit strings of length ten end with 00
|AՈB| = number of bit strings of length ten start with 1 and end with 00
|AՍB| = number of bit strings of length ten either start with 1 or end with 00

Calculation,
number of bit strings of length ten start with 1
first bit out of 10 bits is fixed to 1, and remaining 9 bits have 2 option either 1 or 0
Total possible number of bit strings of length ten start with 1 = 29 = 512

number of bit strings of length ten end with 00
last 2 bits out of 10 bits are fixed to 00, and remaining 8 bits have 2 option either 1 or 0
Total possible number of bit strings of length ten end with 00 =28 = 256

number of bit strings of length ten start with 1 and end with 00
first bit out of 10 bits is fixed to 1 and last 2 bits out of 10 bits are fixed to 00, and remaining 7 bits have 2 option either 1 or 0
Total possible number of bit strings of length ten start with 1 and end with 00 =27 = 128

|AՍB| = A + B – |AՈB|
= 512 + 256 – 128
= 640

Therefore, Number of bit strings of length ten either start with 1 or end with 00 is 640.
So, Option(III) is correct.

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Question .27➡ | NTA UGC NET June 2019
The parallel bus arbitration technique uses an external priority encoder and a decoder. Suppose, a parallel arbiter has 5 bus arbiters. What will be the size of priority encoder and decoder respectively?
i ➥ 4×2, 2×4
ii ➥ 2×4, 4×2
iii ➥ 3×8, 8×3
iv ➥ 8×3, 3×8

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Answer: IV
Explanation:
Priority Encoder: Priority Encoder is a combinational circuit that have 2n inputs and n outputs. The size of Priority Encoder is 2n x n.
Priority Decoder: Priority decoder is a combinational circuit that have n inputs and 2n outputs. The size of Priority Decoder is n x 2n.

Calculation,
It is given, a parallel bus arbiter has 5 bus arbiter.
so, number of bits to represent 5 bus = Гlog25Ⴈ = 3 bits
Priority Encoder
n = 3 bits
Number of inputs to priority encoder = 2n = 23 = 8
Number of outputs to priority encoder = n = 3
Therefore, size of priority encoder = 8 x 3
Priority Decoder
n = 3 bits
Number of inputs to priority decoder = n = 3
Number of outputs to priority decoder = 2n = 23 = 8
Therefore, size of priority decoder = 3 x 8

So, Option(IV) is correct.

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Question .28➡ | NTA UGC NET December 2018
In computers, subtraction is generally carried out by
i ➥ 1’s complement
ii ➥ 10’s complement
iii ➥ 2’s complement
iv ➥ 9’s complement

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Answer: III
Explanation:
In computers, subtraction is generally carried out by 2’s complement.
So, Option(III) is correct.

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Question .29➡ | NTA UGC NET December 2018
The boolean expression A’⋅B+A.B’+A.B is equivalent to
i ➥ A+B
ii ➥ A.B
iii ➥ (A+B)’
iv ➥ A’.B

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Answer: I
Explanation:
=> A’⋅B+A.B’+A.B
=> A’⋅B+A.(B’+B)
=> A’⋅B+A {since, B’+B = 1}
=> (A’ + A) . (B + A)
=> 1 . (B + A)
=> (B + A)
=> A + B
So, Option(I) is correct.

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Question .30➡ | NTA UGC NET December 2018
The relation ≤ and < on a boolean algebra are defined as :
x ≤ y and only if x ∨ y = y
x < y means x ≤ y but x ≠ y
x ≥ y means y ≤ x and
x > y means y <x

Consider the above definitions, which of the following is not true in the boolean algebra ?
(i)If x ≤ y and y ≤ z, then x ≤ z
(ii)If x ≤ y and y ≤ x, then x=y
(iii)If x < y and y < z, then x ≤ y
(iv)If x < y and y < z, then x < y
i ➥ (iv) only
ii ➥ (iii) only
iii ➥ (i) and (ii) only
iv ➥ (ii) and (iii) only

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Answer: II
Explanation:
(i)If x ≤ y and y ≤ z, then x ≤ z (True)
it is by transitive rule.
(ii)If x ≤ y and y ≤ x, then x=y (True)
As x ≤ y , it means x ∨ y = y
and
As y ≤ x , it means y ∨ x = x ∨ y = x
Therefore, x ∨ y = y = y ∨ x = x
(iii)If x < y and y < z, then x ≤ y (False)
As x < y(x less than y), then x ≤ y (x less than equal to y) is incorrect
(iv)If x < y and y < z, then x < y (True)
As x < y, then x < y which is same in both cases.
So, Option(II) is correct.

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Question .31➡ | NTA UGC NET December 2018
Consider the following boolean equations :
(i) wx + w(x + y) + x(x + y)=x+wy
(ii) (wx’(y+xz’)+w’x’)y=x’y

What can you say about the above equations ?
i ➥ Both (i) and (ii) are true
ii ➥ (i) is true and (ii) is false
iii ➥ Both (i) and (ii) are false
iv ➥ (i) is false and (ii) is true

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Answer: I
Explanation:
Let’s take each boolean equation:
(i) wx + w(x + y) + x(x + y)=x+wy
= wx + wx + wy + xx + xy
= wx + wy + x + xy
= x(1 + w + y) + wy
= x + wy
Therefore, equation(i) is True.

(ii) (wx’(y+xz’)+w’x’)y=x’y
= (wx’y + wx’xz’ + w’x’)y
= (wx’y + w’x’)y
= wx’yy + w’x’y
= wx’y + w’x’y
= (w + w’)x’y
= x’y
Therefore, equation(iI) is True.
So, Option(I) is correct.

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Question .32➡ | NTA UGC NET December 2018
Find the boolean expression for the logic circuit shown below :
(1-NAND gate, 2-NOR gate, 3-NOR gate)
Find the boolean expression for the logic circuit shown below : (1-NAND gate, 2-NOR gate, 3-NOR gate)  A)	AB B)	AB’ C)	A’B’ D)	A’B
i ➥ AB
ii ➥ AB’
iii ➥ A’B’
iv ➥ A’B

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Answer: I
Explanation:
Find the boolean expression for the logic circuit shown below : (1-NAND gate, 2-NOR gate, 3-NOR gate)
= [(A.B)’ + (A + B)’]’
= [A’ + B’ + A’B’]’
= [A’ + B'(1 + A’)]’
= [A’ + B’]’
= A.B
So, Option(I) is correct.

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Question .34➡ | NTA UGC NET December 2018
The decimal floating point number -40.1 represented using IEEE-754 32-bit representation and written in hexadecimal form is
i ➥ 0xC2206000
ii ➥ 0xC2006666
iii ➥ 0xC2006000
iv ➥ 0xC2206666

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Answer: IV
Explanation:
IEEE-754 32-bit representation
In the standard format for a single-precision binary number, the sign bit (S) is the left-most bit, the exponent (E) includes the next eight bits, and the mantissa or fractional part (F) includes the remaining 23 bits, as shown next.
The decimal floating point number -40.1 represented using IEEE-754 32-bit representation and written in hexadecimal form is
The eight bits in the exponent represent a biased exponent, which is obtained by adding 127 to the actual exponent.
Calculation,
Given, (-40.1)10
convert the decimal number into binary number
(-40.1)10 = (- 101000 . 00011 0011 0011 0011)2
Normalize above binary number into implicit normalization
(- 1 . 01000 00011 0011 0011 0011 x 25)2
here,
sign bit = 1
because it is negative number
Exponent = 5 + 127 = (132)10 = (1000 0100)2
Mantissa = 01000 00011 0011 0011 0011 0
The decimal floating point number -40.1 represented using IEEE-754 32-bit representation and written in hexadecimal form is
(1100 0010 0000 0110 0110 0110 0110)2
Convert into base 16 representation
0xC206666
So, Option(IV) is correct.

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Question .35➡ | NTA UGC NET December 2018
Which of the following statements are true ?

(i) Every logic network is equivalent to one using just NAND gates or just NOR gates.
(ii) Boolean expressions and logic networks correspond to labelled acyclic digraphs.
(iii) No two Boolean algebras with n atoms are isomorphic.
(iv) Non-zero elements of finite Boolean algebras are not uniquely expressible as joins of atoms.
i ➥ (i) and (iv) only
ii ➥ (i) and (ii) only
iii ➥ (i), (ii) and (iii) only
iv ➥ (ii), (iii) and (iv) only

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Answer: II

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Question .36➡ | NTA UGC NET June 2018
To guarantee correction of upto t errors, the minimum Hamming distance dmin in a block code must be__________.
i ➥ t+1
ii ➥ t−2
iii ➥ 2t−1
iv ➥ 2t+1

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Answer: IV
Explanation:
To guarantee correction of upto t errors, the minimum Hamming distance dmin = t+1
So, Option(I) is correct.

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Question .37➡ | NTA UGC NET June 2018
CMOS is a Computer Chip on the motherboard, which is :
i ➥ RAM
ii ➥ ROM
iii ➥ EPROM
iv ➥ Auxiliary storage

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Answer: I

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Question .38➡ | NTA UGC NET June 2018
In RS flip-flop, the output of the flip-flop at time (t+1) is same as the output at time t, after the occurrence of a clock pulse if :
i ➥ S=R=1
ii ➥ S=0, R=1
iii ➥ S=1, R=0
iv ➥ S=R=0

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Answer: IV

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Question .39➡ | NTA UGC NET June 2018
Match the terms in List – I with the options given in List – II :
Match the terms in List – I with the options given in List – II : (a) Decoder (b)Multiplexer (c)Demultiplexer  (i) 1 line to 2n line
i ➥ (a)-(ii), (b)-(i), (c)-(iii)
ii ➥ (a)-(ii), (b)-(iii), (c)-(i)
iii ➥ (a)-(ii), (b)-(i), (c)-(iv)
iv ➥ (a)-(iv), (b)-(ii), (c)-(i)

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Answer: II

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Question .40➡ | NTA UGC NET June 2018
What does the following logic diagram represent ?
What does the following logic diagram represent ?A ➥ Synchronous Counter B ➥ Ripple Counter C ➥ Combinational Circuit D ➥ Mod 2 Counter
i ➥ Synchronous Counter
ii ➥ Ripple Counter
iii ➥ Combinational Circuit
iv ➥ Mod 2 Counter

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Answer: II

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Question .41➡ | NTA UGC NET June 2018
Perform the following operation for the binary equivalent of the decimal numbers (-14)10+(15)10 The solution in 8 bit representation is :
i ➥ 11100011
ii ➥ 00011101
iii ➥ 10011101
iv ➥ 11110011

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Answer: I

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Question .42➡ | NTA UGC NET June 2018
Simplify the following using K-map : F (A, B, C, D) = Σ (0, 1, 2, 8, 9, 12, 13) + d(A, B, C, D) = Σ (10, 11, 14, 15) d stands for don’t care condition.
i ➥ A+B’D’ + BC
ii ➥ A+B’D’ + B’C’
iii ➥ A’+B’C’
iv ➥ A’+B’C’+B’D’

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Answer: II

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Question .43➡ | NTA UGC NET November 2017 Paper III
Let P, Q, R and S be Propositions. Assume that the equivalences P ⇔ (Q ∨ ¬ Q) and Q ⇔ R hold.Then the truth value of the formula
(P ∧ Q) ⇒ ((P ∧ R) ∨ S) is always:
i ➥ True
ii ➥ False
iii ➥ Same as truth table of Q
iv ➥ Same as truth table of S

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Answer: I

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Question .43➡ | NTA UGC NET November 2017 Paper III
For any binary (n, h) linear code with minimum distance (2t+1) or greater
Q66 (NET Nov 2017 paper III) For any binary (n, h) linear code with minimum distance (2t+1) or greater   A ➥ 2t+1 B ➥ t+1 C ➥ t D ➥ t-1
i ➥ 2t+1
ii ➥ t+1
iii ➥ t
iv ➥ t-1

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Answer: IV

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Question .44➡ | NTA UGC NET November 2017 Paper II
If the time is now 4 O’clock, what will be the time after 101 hours from now ?
i ➥ 9 O’Clock
ii ➥ 8 O’Clock
iii ➥ 5 O’Clock
iv ➥ 4 O’Clock

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Answer: I

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Question 45➡ | NTA UGC NET November 2017 Paper II
Let m=(313)4 and n=(322)4 . Find the base 4 expansion of m+n.
i ➥ (635)4
ii ➥ (32312)4
iii ➥ (21323)4
iv ➥ (1301)4

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Answer: IV

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Question .46➡ | NTA UGC NET November 2017 Paper II
The Boolean function with the Karnaugh map
Q6 (NET Nov 2017 paper II) The Boolean function with the Karnaugh map   is: A ➥ (A+C).D+B B ➥ (A+B).C+D C ➥ (A+D).C+B D ➥ (A+C).B+D
i ➥ (A+C).D+B
ii ➥ (A+B).C+D
iii ➥ (A+D).C+B
iv ➥ (A+C).B+D

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Answer: I

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Question .47➡ | NTA UGC NET November 2017 Paper II
The Octal equivalent of the binary number 1011101011 is :
i ➥ 7353
ii ➥ 1353
iii ➥ 5651
iv ➥ 5657

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Answer: II

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Question .48➡ | NTA UGC NET November 2017 Paper II
Let P and Q be two propositions, ¬ (P ↔ Q) is equivalent to:
i ➥ P ↔ ¬ Q
ii ➥ ¬ P ↔ Q
iii ➥ ¬ P ↔ ¬ Q
iv ➥ Q → P

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Answer: I , II Both(Marks to all)

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Question .49➡ | NTA UGC NET November 2017 Paper II
The output of the following combinational circuit is F:
Q10  (NET Nov 2017 paper II)   The output of the following combinational circuit is F.  The value of F is : A ➥ P1+P’2P3 B ➥ P1+P’2P’3 C ➥ P1 +P2 P’3 D ➥ P’1 +P2 P3
The value of F is :
i ➥ P1+P’2P3
ii ➥ P1+P’2P’3
iii ➥ P1 +P2 P’3
iv ➥ P’1 +P2 P3

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Answer: II

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Question .50➡ | NTA UGC NET January 2017 Paper III
Let C be a binary linear code with minimum distance 2t + 1 then it can correct upto______bits of error.
i ➥ t + 1
ii ➥ t
iii ➥ t – 2
iv ➥ t / 2

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Answer: II

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Question .51➡ | NTA UGC NET January 2017 Paper II
ECL is the fastest of all logic families. High speed in ECL is possible because transistors are used in difference amplifier configuration, in which they are never driven into __.
i ➥ Race condition
ii ➥ Saturation
iii ➥ Delay
iv ➥ High impedance

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Answer: II

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Question .52➡ | NTA UGC NET January 2017 Paper II
A binary 3 bit down counter uses J-K flip-flops, FFi with inputs Ji , Ki and outputs Qi , i=0,1,2 respectively. The minimized expression for the input from following, is
I. J0 = K0 = 0
II. J0 = K0 = 1
III. J1 = K1 = Q0
IV. J1 = K1 =Q’0
V. J2 = K2 = Q1 Q0
VI. J2 = K2 = Q’1 Q’0
i ➥ I,III,V
ii ➥ I,IV,VI
iii ➥ II,III,V
iv ➥ II,IV,VI

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Answer: IV

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Question .53➡ | NTA UGC NET January 2017 Paper II
Convert the octal number 0.4051 into its equivalent decimal number:
i ➥ 0.5100098
ii ➥ 0.2096
iii ➥ 0.52
iv ➥ 0.4192

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Answer: I

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Question .54➡ | NTA UGC NET January 2017 Paper II
The hexadecimal equivalent of the octal number 2357 is :
i ➥ 2EE
ii ➥ 2FF
iii ➥ 4EF
iv ➥ 4FE

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Answer: III

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Question .55➡ | NTA UGC NET January 2017 Paper II
If X is a binary number which is power of 2, then the value of X & (X – 1) is :
i ➥ 11….11
ii ➥ 00…..00
iii ➥ 100…..0
iv ➥ 000……1

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Answer: II

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Question .56➡ | NTA UGC NET August 2016 Paper II
Which of the following logic expressions is incorrect?
i ➥ 1 ⊕ 0 = 1
ii ➥ 1 ⊕ 1 ⊕ 1 = 1
iii ➥ 1 ⊕ 1 ⊕ 0 = 1
iv ➥ 1 ⊕ 1 = 0

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Answer: III

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Question .57➡ | NTA UGC NET August 2016 Paper II
The IEEE-754 double-precision format to represent floating point numbers, has a length of _ bits.
i ➥ 16
ii ➥ 32
iii ➥ 48
iv ➥ 64

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Answer: IV

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Question .58➡ | NTA UGC NET August 2016 Paper II
Simplified Boolean equation for the following truth table is:
Simplified Boolean equation for the following truth table is:   A	F = yz’ + y’z B	F = xy’ + x’y C	F = x’z + xz’ D	F = x’z + xz’ + xyz
i ➥ F = yz’ + y’z
ii ➥ F = xy’ + x’y
iii ➥ F = x’z + xz’
iv ➥ F = x’z + xz’ + xyz

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Answer: III

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Question .59➡ | NTA UGC NET August 2016 Paper II
The simplified form of a Boolean equation (AB’ + AB’C + AC) (A’C’ + B’) is :
i ➥ AB’
ii ➥ AB’C
iii ➥ A’B
iv ➥ ABC

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Answer: I

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Question .60➡ | NTA UGC NET August 2016 Paper II
In a positive-edge-triggered JK flip-flop, if J and K both are high then the output will be _________ on the rising edge of the clock.
i ➥ No change
ii ➥ Set
iii ➥ Reset
iv ➥ Toggle

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Answer: IV

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Question .61➡ | NTA UGC NET August 2016 Paper III
A ripple counter is a :
i ➥ Synchronous Counter
ii ➥ Asynchronous counter
iii ➥ Parallel counter
iv ➥ None of the above

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Answer: II

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Question .62➡ | NTA UGC NET August 2016 Paper II
The output of the following combinational circuit.
NET Aug 2016 paper III The output of the following combinational circuit. X.Y X+Y X⊕Y (X⊕Y)’
i ➥ X.Y
ii ➥ X+Y
iii ➥ X⊕Y
iv ➥ (X⊕Y)’

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Answer: IV

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Question .63➡ | NTA UGC NET July 2016 Paper II
The octal number 326.4 is equivalent to
i ➥ (214.2)10 and (D6.8))16
ii ➥ (212.5)10 and (D6.8))16
iii ➥ (214.5)10 and (D6.8))16
iv ➥ (214.5)10 and (D6.4))16

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Answer: III

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Question .64➡ | NTA UGC NET July 2016 Paper II
Which of the following is the most efficient to perform arithmetic operations on the numbers?
i ➥ Sign-magnitude
ii ➥ 1’s complement
iii ➥ 2’s complement
iv ➥ 9’s complement

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Answer: III

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Question .65➡ | NTA UGC NET July 2016 Paper II
The Karnaugh map for a Boolean function is given as
The Karnaugh map for a Boolean function is given as   The simplified Boolean equation for the above Karnaugh Map is A	AB + CD + AB’ + AD B	AB + AC + AD + BCD C	AB + AD + BC + ACD D	AB + AC + BC + BCD Net July 2016 question
The simplified Boolean equation for the above Karnaugh Map is
i ➥ AB + CD + AB’ + AD
ii ➥ AB + AC + AD + BCD
iii ➥ AB + AD + BC + ACD
iv ➥ AB + AC + BC + BCD

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Answer: II

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Question .66➡ | NTA UGC NET July 2016 Paper II
Which of the following logic operations is performed by the following given combinational circuit?
Which of the following logic operations is performed by the following given combinational circuit?   A	EXCLUSIVE-OR B	EXCLUSIVE-NOR C	NAND net july 2016
i ➥ EXCLUSIVE-OR
ii ➥ EXCLUSIVE-NOR
iii ➥ NAND
iv ➥ NOR

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Answer: I

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Question .67➡ | NTA UGC NET July 2016 Paper II
Match the following:
Match the following: a) controlled inverter b) full adder c) half adder d) binary adder   A	a-iii, b-ii, c-iv, d-i B	a-ii, b-iv, c-i, d-iii C	a-ii, b-i, c-iv, d-iii D	a-iii, b-i, c-iv, d-ii
i ➥ a-iii, b-ii, c-iv, d-i
ii ➥ a-ii, b-iv, c-i, d-iii
iii ➥ a-ii, b-i, c-iv, d-iii
iv ➥ a-iii, b-i, c-iv, d-ii

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Answer: IV

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Question .68➡ | NTA UGC NET July 2016 Paper III
Which of the following is a sequential circuit?
i ➥ Multiplexer
ii ➥ Decoder
iii ➥ Counter
iv ➥ Full adder

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Answer: III

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Question .69➡ | NTA UGC NET December 2015 Paper III
The three outputs X1X2X3 from the 8 X 3 priority encoder are used to provide a vector address of the form 101X1X2X300. What is the second highest priority vector address in hexadecimal if the vector addresses are starting from the one with the highest priority ?
i ➥ BC
ii ➥ A4
iii ➥ BD
iv ➥ AC

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Answer: II

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Question .70➡ | NTA UGC NET December 2014 Paper II
The BCD adder to add two decimal digits needs minimum of
i ➥ 6 full adders and 2 half adders
ii ➥ 5 full adders and 3 half adders
iii ➥ 4 full adders and 3 half adders
iv ➥ 5 full adders and 2 half adders

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Answer: IV

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Question .71➡ | NTA UGC NET December 2014 Paper II
The Excess-3 decimal code is a self-complementing code because
i ➥ The binary sum of a code and its 9’s complement is equal to 9.
ii ➥ It is a weighted code
iii ➥ Complement can be generated by inverting each bit pattern
iv ➥ The binary sum of a code and its 10’s complement is equal to 9

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Answer: III

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Question .72➡ | NTA UGC NET December 2014 Paper II
The range of representable normalized numbers in the floating point binary fractional representation in a 32-bit word with 1-bit sign, 8-bit excess 128 biased exponent and 23-bit mantissa is
i ➥ 2-128 to (1 – 2–23 ) * 2127
ii ➥ (1 – 2–23 ) * 2-127 to 2128
iii ➥ (1 – 2–23 ) * 2–127 to 223
iv ➥ 2–129 to (1 – 2–23 ) * 2127

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Answer: IV

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Question .73➡ | NTA UGC NET June 2014 Paper II
A Boolean function F is called self-dual if and only if F(x1, x2, … xn) = F (͞x1,͞x2, …͞xn) How many Boolean functions of degree n are self-dual ?
i ➥ 2n
ii ➥ (2)2^n
iii ➥ (2)n^2
iv ➥ (2)(2^(n-1))

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Answer: IV

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Question .74➡ | NTA UGC NET June 2014 Paper II
Which of the following statement(s) is (are) not correct ?

i. The 2’s complement of 0 is 0.
ii. In 2’s complement, the left most bit cannot be used to express a quantity.
iii. For an n-bit word (2’s complement) which includes the sign bit, there are 2n–1 positive integers, 2n+1 negative integers and one 0 for a total of 2n unique states.
iv. In 2’s complement the significant information is contained in the 1’s of positive numbers and 0’s of the negative numbers.
i ➥ i & iv
ii ➥ i & ii
iii ➥ iii
iv ➥ iv

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Answer: III

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Question .75➡ | NTA UGC NET June 2014 Paper III
The output of a sequential circuit depends on
i ➥ Present input only
ii ➥ Both present and past input
iii ➥ Past output only
iv ➥ None of the above

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Answer: II

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Question .76➡ | NTA UGC NET June 2014 Paper III
Which of the following flip-flops is free from race condition ?
i ➥ T flip-flop
ii ➥ SR flip-flop
iii ➥ Master-slave JK flip-flop
iv ➥ None of the above

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Answer: III

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Question .77➡ | NTA UGC NET June 2014 Paper III
A terminal multiplexer has six 1200 bps terminals and ‘n’ 300 bps terminals connected to it. If the outgoing line is 9600 bps, what is the value of n ?
i ➥ 4
ii ➥ 8
iii ➥ 16
iv ➥ 28

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Answer: II

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Question .78➡ | NTA UGC NET December 2013 Paper III
Which of the following statements are true ?

a. A circuit that adds two bits, producing a sum bit and a carry bit is called half adder.
b. A circuit that adds two bits, producing a sum bit and a carry bit is called full adder.
c. A circuit that adds two bits and a carry bit producing a sum bit and a carry bit is called full adder.
d. A device that accepts the value of a Boolean variable as input and produces its complement is called an inverter.
i ➥ a and b
ii ➥ b and c
iii ➥ a, b and c
iv ➥ a, c and d

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Answer: IV

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Question .79➡ | NTA UGC NET December 2013 Paper III
What will be the output of the following logic diagram?
1.	What will be the output of the following logic diagram? net decemver 2013
i ➥ x OR y
ii ➥ x AND y
iii ➥ x XOR y
iv ➥ x XNOR y

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Answer: III

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Question .80➡ | NTA UGC NET December 2013 Paper III
What are the final values of Q1 and Q0 after 4 clock cycles, if initial values are 00 in the sequential circuit shown below:
43.	What are the final values of Q1 and Q0 after 4 clock cycles, if initial values are 00 in the sequential circuit shown below:
i ➥ 11
ii ➥ 10
iii ➥ 01
iv ➥ 00

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Answer: IV

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Question .81➡ | NTA UGC NET December 2013 Paper III
Synchronization is achieved by a timing device called_________ a which generates a periodic train of ________.
i ➥ clock generator, clock pulse
ii ➥ master generator, clock pulse
iii ➥ generator, clock
iv ➥ master clock generator, clock pulse

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Answer: I, IV
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