GATE CSE Digital Logic Design PYQ

GATE CSE Digital Logic Design PYQ

Q1➡ | GATE 2021 set-1
Let the representation of a number in base 3 be 210. What is the hexadecimal representation of the number?
i ➥ 528
ii ➥ D2
iii ➥ 15
iv ➥ 21

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Answer: III
Explanation:
Given,
(210)3
Calculation,
(210)3
First convert it into decimal represenation
= 2 x 32 + 1 x 31 + 0 x 30
= 2 x 9 + 3
= (21)10
now convert it into base 2 representation
= (10101)2
now make a pair of 4 bits and then convert 4 bits into decimal representation to get hexadecimal representation because log216 = 4 bits
=(0001 0101)2
= (15)16
So, Option(II) is correct.

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Q2➡ | GATE 2021 set-1
Consider the following representation of a number in IEEE 754 single-precision floating point format with a bias of 127.
S : 1
E : 10000001
F : 11110000000000000000000
Here S, E and F denote the sign, exponent and fraction components of the floating point representation.
The decimal value corresponding to the above representation (rounded to 2 decimal places) is _________.

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Answer: -7.75
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Q3➡ | GATE 2021 set-1
Consider a 3-bit counter, designed using T flip-flops, as shown below:

Assuming the initial state of the counter given by PQR as 000, what are the next three states?
i ➥ 011, 101, 111
ii ➥ 001, 010, 000
iii ➥ 001, 010, 111
iv ➥ 011, 101, 000

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Answer: IV
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Q4➡ | GATE 2021 set-1

Which one of the following choices gives the correct values of x and y?
i ➥ x is 1 and y is 0
ii ➥ x is 0 and y is 0
iii ➥ x is 0 and y is 1
iv ➥ x is 1 and y is 1

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Answer: II
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Q5➡ | GATE 2021 set-1
Consider the following Boolean expression GATE CSE 2021 set 1
i ➥
ii ➥
iii ➥
iv ➥

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Answer: i,iii,iv
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Q6➡ | GATE 2021 set-2
Which one of the following circuits implements the Boolean function given below?
f(x,y,z) = m0 + m1 + m3 + m4 + m5 +m6 ,
where mi is the ith minterm.
i ➥
ii ➥
iii ➥
iv ➥

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Answer: I
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Q7➡ | GATE 2021 set-2
The format of the single-precision floating-point representation of a real number as per the IEEE 754 standard is as follows:

Which one of the following choices is correct with respect to the smallest normalized positive number represented using the standard?
i ➥ exponent = 00000001 and mantissa = 00000000000000000000001
ii ➥ exponent = 00000000 and mantissa = 00000000000000000000000
iii ➥ exponent = 00000000 and mantissa = 00000000000000000000001
iv ➥ exponent = 00000001 and mantissa = 00000000000000000000000

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Answer: IV
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Q8➡ | GATE 2021 set-2
If x and y are two decimal digits and (0.1101)2=(0.8xy5)10, the decimal value of x+y is _____.

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Answer: 3
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Q9➡ | GATE 2021 set-2
If the numerical value of a 2-byte unsigned integer on a little endian computer is 255 more than that on a big endian computer, which of the following choices represent(s) the unsigned integer on a little endian computer?
i ➥ 0x0100
ii ➥ 0x6665
iii ➥ 0x4243
iv ➥ 0x0001

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Answer: I, II
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Q10➡ | GATE 2021 set-2
Consider a Boolean function f(w, x, y, z) such that
f(w, 0, 0, z) = 1
f(1, x, 1, z) = x + z
f(w, 1, y, z) = wz + y
The number of literals in the minimal sum-of-products expression of f is _______.

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Answer: 6
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Q11➡ | GATE 2020
If there are m input lines and n output lines for a decoder that is used to uniquely address a byte addressable 1 KB RAM, then the minimum value of m + n is ______.

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Answer: 1034
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Q12➡ | GATE 2020
A multiplexer is placed between a group of 32 registers and an accumulator to regulate data movement such that at any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is _______.

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Answer: 5
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Q13➡ | GATE 2020
Consider three registers R1, R2 and R3 that store numbers in IEEE-754 single precision floating point format. Assume that R1 and R2 contain the values (in hexadecimal notation) 0x42200000 and 0xC1200000, respectively.
If R3 = R1/R2, what is the value stored in R3?
i ➥ 0x83400000
ii ➥ 0xC8500000
iii ➥ 0xC0800000
iv ➥ 0x40800000

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Answer: III
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Q14➡ | GATE 2020
Consider the Boolean function z(a,b,c)

Which one of the following minterm lists represents the circuit given above ?
i ➥ Z = ∑(2,3,5)
ii ➥ Z = ∑(0,1,3,7)
iii ➥ Z = ∑(1,4,5,6,7).
iv ➥ Z = ∑(2,4,5,6,7).

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Answer: III
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Q15➡ | GATE 2019
Which one of the following is NOT a valid identity?
i ➥ x ⊕ y = x + y, if xy = 0
ii ➥ (x ⊕ y) ⊕ z = x ⊕ (y ⊕ z)
iii ➥ x ⊕ y = (xy + x’y’)’
iv ➥ (x + y) ⊕ z = x ⊕ (y + z)

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Answer: IV
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Q16➡ | GATE 2019
In 16-bit 2’s complement representation, the decimal number -28 is:
i ➥ 1000 0000 1110 0100
ii ➥ 1111 1111 1110 0100
iii ➥ 1111 1111 0001 1100
iv ➥ 0000 0000 1110 0100

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Answer: II
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Q17➡ | GATE 2019
Two numbers are chosen independently and uniformly at random from the set {1, 2, …, 13}. The probability (rounded off to 3 decimal places) that their 4-bit (unsigned) binary representations have the same most significant bit is ________.

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Answer: 0.502 to 0.504
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Q18➡ | GATE 2019
Consider three 4-variable functions f1, f2 and f3, which are expressed in sum-of-minterms as
f1 = Σ(0, 2, 5, 8, 14), f2 = Σ(2, 3, 6, 8, 14, 15), f3 = Σ(2, 7, 11, 14)
For the following circuit with one AND gate and one XOR gate, the output function f can be expressed as:
i ➥ Σ (0, 2, 3, 5, 6, 7, 8, 11, 14, 15)
ii ➥ Σ (7, 8, 11)
iii ➥ Σ (2, 14)
iv ➥ Σ (2, 7, 8, 11, 14)

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Answer: II
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Q19➡ | GATE 2019
What is the minimum number of 2-input NOR gates required to implement a 4-variable function function expressed in sum-of-minterms form as f = Σ(0, 2, 5, 7, 8, 10, 13, 15)? Assume that all the inputs and their complements are available.

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Answer: 3
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Q20➡ | GATE 2018
Let ⊕ and ⊙ denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT CORRECT?
i ➥
ii ➥
iii ➥
iv ➥

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Answer: I
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Q21➡ | GATE 2018
Consider the sequential circuit shown in the figure, where both flip-flops used are positive edge-triggered D flip-flops.

The number of states in the state transition diagram of this circuit that have a transition back to the same state on some value of “in” is _____.

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Answer: 2
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Q22➡ | GATE 2018
Consider the unsigned 8-bit fixed point binary number representation below.
b7 b6 b5 b4 b3 . b2 b1 b0
where the position of the binary point is between b3 and b2 . Assume b7 is the most significant bit. Some of the decimal numbers listed below cannot be represented exactly in the above representation:

(i) 31.500 (ii) 0.875 (iii) 12.100 (iv) 3.001
Which one of the following statements is true?
i ➥ None of (i), (ii), (iii), (iv) can be exactly represented
ii ➥ Only (ii) cannot be exactly represented
iii ➥ Only (iii) and (iv) cannot be exactly represented
iv ➥ Only (i) and (ii) cannot be exactly represented

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Answer: III
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Q23➡ | GATE 2018
Consider the minterm list form of a Boolean function F given below.

Here, m denotes a minterm and d denotes a don’t care term. The number of essential prime implicants of the function F is _______.

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Answer: 3
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Q24➡ | GATE 2017 Set-1
When two 8-bit numbers A7…A0 and B7…B0 in 2’s complement representation (with A0 and B0 as the least significant bits) are added using a ripple-carry adder, the sum bits obtained are S7…S0 and the carry bits are C7…C0. An overflow is said to have occurred if
i ➥ (A7 . B7 . S7‘ + A7‘. B7‘. S7) is 1
ii ➥ the carry bit C7 is 1
iii ➥ (A0 . B0 . S0‘ + A0‘. B0‘. S0) is 1
iv ➥ all the carry bits (C7,…,C0) are 1

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Answer: I
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Q25➡ | GATE 2017 Set-1
The n-bit fixed-point representation of an unsigned real number X uses f bits for the fraction part. Let i = n-f. The range of decimal values for X in this representation is
i ➥ 0 to 2i
ii ➥ 0 to (2i – 2-f )
iii ➥ 2-f to 2i
iv ➥ 2-f to (2i – 2-f)

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Answer: II
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Q26➡ | GATE 2017 Set-1
Consider the Karnaugh map given below, where X represents “don’t care” and blank represents 0.
Assume for all inputs (a, b, c, d) , the respective complements (a’, b’, c’, d’) are also available. The above logic is implemented using 2-input NOR gates only. The minimum number of gates required is ___________.

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Answer: 1.0
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Q27➡ | GATE 2017 Set-1
Consider a combination of T and D flip-flops connected as shown below. The output of the D flip-flop is connected to the input of the T flip-flop and the output of the T flip-flop is connected to the input of the D flip-flop:

Initially, both Q0 and Q1 are set to 1 (before the 1st clock cycle). The outputs
i ➥ Q1Q0 after the 3rd cycle are 00 and after the 4th cycle are 11 respectively
ii ➥ Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 00 respectively
iii ➥ Q1Q0 after the 3rd cycle are 01 and after the 4th cycle are 01 respectively
iv ➥ Q1Q0 after the 3rd cycle are 11 and after the 4th cycle are 01 respectively

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Answer: IV
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Q28➡ | GATE 2017 Set-2
The representation of the value of a 16-bit unsigned integer X in hexadecimal number system is BCA9. The representation of the value of X in octal number system is:
i ➥ 136252
ii ➥ 571247
iii ➥ 736251
iv ➥ 136251

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Answer: IV
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Q29➡ | GATE 2017 Set-2
Given the following binary number in 32-bit (single precision) IEEE-754 format:
00111110011011010000000000000000
The decimal value closest to this floating-point number is
i ➥ 2.27 × 10-1
ii ➥ 1.45 × 101
iii ➥ 1.45 × 10-1
iv ➥ 2.27 × 101

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Answer: I
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Q30➡ | GATE 2017 Set-2
Consider a quadratic equation x2 – 13x + 36 = 0 with coefficients in a base b. The solutions of this equation in the same base b are x = 5 and x = 6. Then b=_________.

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Answer: 8
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Q31➡ | GATE 2017 Set-2
Given f(w,x,y,z) = Σm(0,1,2,3,7,8,10) + Σd(5,6,11,15), where d represents the don’t-care condition in Karnaugh maps. Which of the following is a minimum product-of-sums (POS) form of f(w,x,y,z)?
i ➥ f = (w’ + z’) (x’ + z)
ii ➥ f = (w’ + z) (x + z)
iii ➥ f = (w + z) (x’ + z)
iv ➥ f = (w + z’) (x’ + z)

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Answer: I
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Q32➡ | GATE 2017 Set-2
If w, x, y, z are Boolean variables, then which one of the following is INCORRECT?
i ➥ wx + w(x + y) + x(x + y) = x + wy
ii ➥
iii ➥
iv ➥ (w + y)(wxy + wyz) = wxy + wyz

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Answer: III
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Q33➡ | GATE 2017 Set-2
Consider a binary code that consists of only four valid code words as given below:
00000, 01011, 10101, 11110
Let the minimum Hamming distance of the code be p and the maximum number of erroneous bits that can be corrected by the code be q. Then the values of p and q are
i ➥ p=4 and q=2
ii ➥ p=4 and q=1
iii ➥ p=3 and q=2
iv ➥ p=3 and q=1

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Answer: IV
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Q38➡ | GATE 2017 Set-2
The next state table of a 2-bit saturating up-counter is given below.
The counter is built as a synchronous sequential circuit using T flip-flops. The expressions for T1 and T0 are
i ➥ T1=Q1Q0 , T0 = Q’1Q’0
ii ➥ T1=Q’1Q0 , T0 = Q’1 + Q’0
iii ➥ T1=Q1 + Q0 , T0 = Q’1 + Q’0
iv ➥ T1=Q’1Q0 , T0 = Q1 + Q0

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Answer: II
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Q39➡ | GATE 2016 Set-1
Consider the Boolean operator with the following properties:
x # 0 = x , x # 1 = x’ , x # x = 0 , x # x’ = 1
Then x#y is equivalent to
i ➥ xy’ + x’y
ii ➥ xy’ + x’y’
iii ➥ x’y + xy
iv ➥ xy + x’y’

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Answer: I
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Q40➡ | GATE 2016 Set-1
The 16-bit 2’s complement representation of an integer is 1111 1111 1111 0101; its decimal representation is ___________.

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Answer: -11
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Q41➡ | GATE 2016 Set-1
We want to design a synchronous counter that counts the sequence 0-1-0-2-0-3 and then repeats. The minimum number of J-K flip-flops required to implement this counter is _________.

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Answer: 4
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Q42➡ | GATE 2016 Set-1
Consider the two cascaded 2-to-1 multiplexers as shown in the figure.

The minimal sum of products form of the output X is
i ➥ P’Q’ + PQR
ii ➥ P’Q + QR
iii ➥ PQ + P’Q’R
iv ➥ Q’R’ + PQR

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Answer: IV
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Q43➡ | GATE 2016 Set-1
Consider a carry lookahead adder for adding two n-bit integers, built using gates of fan-in at most two. The time to perform addition using this adder is __________.
i ➥ Θ(1)
ii ➥ Θ(log(n))
iii ➥ Θ(√n)
iv ➥ Θ(n)

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Answer: II
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Q44➡ | GATE 2016 Set-2
Consider an eight-bit ripple-carry adder for computing the sum of A and B, where A and B are integers represented in 2’s complement form.
If the decimal value of A is one, the decimal value of B that leads to the longest latency for the sum to stabilize is ________.

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Answer: -11
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Q45➡ | GATE 2016 Set-2
Let, x1⊕x2⊕x3⊕x4 = 0 where x1, x2, x3, x4 are Boolean variables, and ⊕ is the XOR operator. Which one of the following must always be TRUE?
i ➥ x1x2x3x4 = 0
ii ➥ x1x3+x2 = 0
iii ➥ x1‘⊕x3‘ = x2‘⊕x4
iv ➥ x1 + x2 + x3 + x4 = 0

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Answer: III
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Q46➡ | GATE 2016 Set-2
Let X be the number of distinct 16-bit integers in 2’s complement representation. Let Y be the number of distinct 16-bit integers in sign magnitude representation.
Then X-Y is _____ .

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Answer: 1
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Q47➡ | GATE 2015 Set-1
Consider a 4-bit Johnson counter with an initial value of 0000. The counting sequence of this counter is
i ➥ 0, 1, 3, 7, 15, 14, 12, 8, 0
ii ➥ 0, 1, 3, 5, 7, 9, 11, 13, 15, 0
iii ➥ 0, 2, 4, 6, 8, 10, 12, 14, 0
iv ➥ 0, 8, 12, 14, 15, 7, 3, 1, 0

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Answer: IV
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Q48➡ | GATE 2015 Set-1
The binary operator ≠ is defined by the following truth table

Which one of the following is true about the binary operator ≠?
i ➥ Both commutative and associative
ii ➥ Commutative but not associative
iii ➥ Not commutative but associative
iv ➥ Neither commutative nor associative

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Answer: I
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Q49➡ | GATE 2015 Set-1
A positive edge-triggered D flip-flop is connected to a positive edge-triggered JK flipflop as follows. The Q output of the D flip-flop is connected to both the J and K inputs of the JK flip-flop, while the Q output of the JK flip-flop is connected to the input of the D flip-flop. Initially, the output of the D flip-flop is set to logic one and the output of the JK flip-flop is cleared. Which one of the following is the bit sequence (including the initial state) generated at the Q output of the JK flip-flop when the flip-flops are connected to a free-running common clock? Assume that J = K = 1 is the toggle mode and J = K = 0 is the state-holding mode of the JK flip-flop. Both the flip-flops have non-zero propagation delays.
i ➥ 0110110…
ii ➥ 0100100…
iii ➥ 011101110…
iv ➥ 011001100…

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Answer: I
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Q50➡ | GATE 2015 Set-2
The minimum number of JK flip-flops required to construct a synchronous counter with the count sequence (0, 0, 1, 1, 2, 2, 3, 3, 0, 0,……) is _______.

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Answer: 3
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Q51➡ | GATE 2015 Set-2
The number of min-terms after minimizing the following Boolean expression is ________.
[D′ + AB′ + A′C + AC′D + A′C′D]′

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Answer: 1
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Q52➡ | GATE 2015 Set-2
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate. The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is _________.

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Answer: 19.2
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Q53➡ | GATE 2015 Set-3

Let # be a binary operator defined as
X # Y = X′ + Y′ where X and Y are Boolean variables. Consider the following two statements.
S1: (P # Q) # R = P # (Q # R)
S2: Q # R = R # Q
Which of the following is/are true for the Boolean variables P, Q and R?
i ➥ Only S1 is True
ii ➥ Only S2 is True
iii ➥ Both S1 and S2 are True
iv ➥ Neither S1 nor S2 are True

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Answer: II
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Q54➡ | GATE 2015 Set-3
Consider the equation (43)x = (y3)8 where x and y are unknown. The number of possible solutions is_______.

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Answer: 5
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Q55➡ | GATE 2015 Set-3
The total number of prime implicants of the function f(w,x,y,z) = Σ(0, 2, 4, 5, 6, 10) is________.

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Answer: 3
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Q56➡ | GATE 2014 Set-1
Consider the following Boolean expression for F:
F(P, Q, R, S) = PQ + P’QR + P’QR’S
The minimal sum-of-products form of F is
i ➥ PQ + QR + QS
ii ➥ P +Q +R + S
iii ➥ P’+ Q’+ R’+S’
iv ➥ P’R + P’R’S + P

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Answer: I
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Q57➡ | GATE 2014 Set-1
The base (or radix) of the number system such that the following equation holds is________________.

312/20 = 13.1

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Answer: 5
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Q58➡ | GATE 2014 Set-2
The dual of a Boolean function F(x1, x2,…, xn, +, ∙ , ′ ), written as FD, is the same expression as that of F with + and swapped. F is said to be self-dual if F = FD. The number of self-dual functions with n Boolean variables is
i ➥ 2n
ii ➥ 2n–1
iii ➥ 22^n
iv ➥ 22^n—1

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Answer: IV
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Q59➡ | GATE 2014 Set-2
Let k = 2n. A circuit is built by giving the output of an n-bit binary counter as input to an n-to-2n bit decoder. This circuit is equivalent to a
i ➥ k-bit binary up counter.
ii ➥ k-bit binary down counter.
iii ➥ k-bit ring counter.
iv ➥ k-bit Johnson counter.

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Answer: 612 to 613
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Q60➡ | GATE 2014 Set-2
Consider the equation (123)5 = (x8)y with x and y as unknown. The number of possible solutions is_______.

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Answer: 3
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Q61➡ | GATE 2014 Set-2
The value of a float type variable is represented using the single-precision 32-bit floating point format of IEEE-754 standard that uses 1 bit for sign, 8 bits for biased exponent and 23 bits for mantissa. A float type variable X is assigned the decimal value of −14.25. The representation of X in hexadecimal notation is
i ➥ C1640000H
ii ➥ 416C0000H
iii ➥ 41640000H
iv ➥ C16C0000H.

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Answer: I
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Q62➡ | GATE 2014 Set-2
Which one of the following Boolean expressions is NOT a tautology?
i ➥ ((a ⟶ b) ∧ (b ⟶ c)) ⟶ (a ⟶ c)
ii ➥ (a ⟷ c) ⟶ (∽ b ⟶ (a ∧ c))
iii ➥ (a ∧ b ∧ c) ⟶ (c ∨ a)
iv ➥ a ⟶ (b ⟶ a)

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Answer: II
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Q63➡ | GATE 2014 Set-3
Consider the following minterm expression for F:
F(P,Q,R,S) = Σ0,2,5,7,8,10,13,15
The minterms 2, 7, 8 and 13 are ‘do not care’ terms. The minimal sum-of-products form for F is:
i ➥ QS’ + Q’S
ii ➥ Q’S’ + QS
iii ➥ Q’R’S’ + Q’RS’ +QR’S +QRS
iv ➥ P’Q’S’ + P’QS + PQS + PQ’S’

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Answer: II
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Q64➡ | GATE 2014 Set-3
Consider the following combinational function block involving four Boolean variables x, y, a, b where x, a, b are inputs and y is the output.

Which one of the following digital logic blocks is the most suitable for implementing this function?
i ➥ Full adder
ii ➥ Priority encoder
iii ➥ Multiplexor
iv ➥ Flip-flop

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Answer: III
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Q65➡ | GATE 2014 Set-3

The above synchronous sequential circuit built using JK flip-flops is initialized with Q2Q1QO = 000. The state sequence for this circuit for the next 3 clock cycles is
i ➥ 001, 010, 011
ii ➥ 111, 110, 101
iii ➥ 100, 110, 111
iv ➥ 100, 011, 001

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Answer: III
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Q66➡ | GATE 2014 Set-3
Let ⊕ denote the Exclusive OR (XOR) operation. Let ‘1’ and ‘0’ denote the binary constants. Consider the following Boolean expression for F over two variables P and Q:
F(P, Q) = ((1⨁P)⨁(P⨁Q)) ⨁ ((P⨁Q)⨁(Q⨁0))
The equivalent expression for F is
i ➥ P+Q
ii ➥
iii ➥ P⨁Q
iv ➥

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Answer: IV
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Q67➡ | GATE 2013
The smallest integer that can be represented by an 8-bit number in 2’s complement form is
i ➥ -256
ii ➥ -128
iii ➥ -127
iv ➥ 0

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Answer: II
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Q68➡ | GATE 2013
In the following truth table, V = 1 if and only if the input is valid.

What function does the truth table represent?
i ➥ Priority encoder
ii ➥ Decoder
iii ➥ Multiplexer
iv ➥ Demultiplexer

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Answer: I
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Q69➡ | GATE 2013
Which one of the following expressions does NOT represent exclusive NOR of x and y?
i ➥ xy+x’y’
ii ➥ x⊕y’
iii ➥ x’⊕y
iv ➥ x’⊕y’

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Answer: IV
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Q70➡ | GATE 2012
The truth table

represents the Boolean function
i ➥ X
ii ➥ X + Y
iii ➥ X ⊕ Y
iv ➥ Y

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Answer: I
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Q71➡ | GATE 2012
The decimal value 0.5 in IEEE single precision floating point representation has
i ➥ fraction bits of 000…000 and exponent value of 0
ii ➥ fraction bits of 000…000 and exponent value of −1
iii ➥ fraction bits of 100…000 and exponent value of 0
iv ➥ no exact representation

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Answer: II
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Q72➡ | GATE 2012
The amount of ROM needed to implement a 4 bit multiplier is
i ➥ 64 bits
ii ➥ 128 bits
iii ➥ 1 Kbits
iv ➥ 2 Kbits

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Answer: IV
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Q73➡ | GATE 2012
What is the minimal form of the karnaugh map shown below? Assume that X denotes a don’t care term
i ➥ b’d’
ii ➥ b’d’+b’c’
iii ➥ b’d’+ab’c’d
iv ➥ b’d’+b’c’+c’d’

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Answer: II
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Q74➡ | GATE 2011
Which one of the following circuits is NOT equivalent to a 2-input XNOR (exclusive NOR) gate?
i ➥
ii ➥
iii ➥
iv ➥

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Answer: IV
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Q75➡ | GATE 2011
The simplified SOP (sum of product) form of the boolean expression
(P + Q’ + R’) . (P + Q’ +R) . (P + Q + R’)
i ➥ (P’.Q + R’)
ii ➥ (P+Q’.R’)
iii ➥ (P’.Q + R)
iv ➥ (P.Q + R)

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Answer: II
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Q76➡ | GATE 2011
The minimum number of D flip-flops needed to design a mod-258 counter is
i ➥ 9
ii ➥ 8
iii ➥ 512
iv ➥ 258

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Answer: I
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Q77➡ | GATE 2011
Common Data for Questions 77 and 78:
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

If at some instance prior to the occurrence of the clock edge, P, Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?
i ➥ 000
ii ➥ 001
iii ➥ 010
iv ➥ 011

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Answer: IV
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Q78➡ | GATE 2011
Common Data for Questions 77 and 78:
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration.

If all the flip-flops were reset to O at power on, what is the total number of distinct outputs (states) represented by PQR generated by the counter?
i ➥ 3
ii ➥ 4
iii ➥ 5
iv ➥ 6

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Answer: II
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Q79➡ | GATE 2010
The minterm expansion of f(P,Q,R) = PQ +QR’ +PR’ is.
i ➥ m2+m4+m6+m7
ii ➥ m0+m1+m3+m5
iii ➥ m0+m1+m6+m7
iv ➥ m2+m3+m4+m5

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Answer: I
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Q80➡ | GATE 2010
P is a 16-bit signed integer. The 2’s complement representation of P is (F87B)16. The 2’s complement representation of 8*P is
i ➥ (C3D8)16
ii ➥ (187B)16
iii ➥ (F878)16
iv ➥ (987B)16

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Answer: I
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Q82➡ | GATE 2010
The Boolean expression for the output ‘f’ of the multiplexer shown below.
i ➥
ii ➥
iii ➥
iv ➥

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Answer: II
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Q83➡ | GATE 2010
What is the Boolean expression for the output f of the combinational logic circuit of NOR gates given below?
i ➥
ii ➥
iii ➥
iv ➥

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Answer: I
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Q84➡ | GATE 2010
In the sequential circuit shown below,if the initial value of the output Q1Q0 is 00,what are the next four values of Q1Q0?
i ➥ 11, 10, 01, 00
ii ➥ 10, 11, 01, 00
iii ➥ 10, 00, 01, 11
iv ➥ 11, 10, 00, 01

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Answer: I
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