Memory hierarchy of COA| UGC NET|GATE

Q1➡ |
The hit ratio of cache memory is the percentage of access (reads and writes)for which data are found in the cache. Write-through, Write-back are two main policies for memory updation. write-allocation is a policy whereby a cache line is allocated and loaded on a write miss. If it is assumed that write-allocation is always used, which of the following is true.
i ➥ Write-through can only be employed in set-associative memory
ii ➥ The percentage of write operations resulting in a main memory operation will never be larger for Write-back than for Write-through
iii ➥ Write through usually results in a better hit ratio than write-back
iv ➥ Write-back usually results in a better hit ratio than write-through

Answer- II

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Q2➡ |
Which of the following statements related to Cache memory organization is FALSE?
i ➥ For direct mapping, no replacement algorithm is needed.
ii ➥ In “write back” approach, updates are made only in the cache and it minimizes memory writes.
iii ➥ Least Recently Used (LRU) replacement algorithm can be used in associative and set associative mappings.
iv ➥ In “write through” approach. main memory content is always invalid.

Answer- IV

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Q3➡ |
Which of the following is an efficient method of cache updating?
i ➥ Write through
ii ➥ Snoopy writes
iii ➥ Buffered write
iv ➥ Write within

Answer- II

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Q4➡ |
A page table is maintained partially in cache memory with a hit ratio of 80%. Give the following, what is the Effective Access Time. Cache lookup takes 5 nanosec and memory access time is 100 nanosec.
i ➥ 25 nanosec
ii ➥ 105 nanosec
iii ➥ 45 nanosec
iv ➥ 125 nanosec

Answer- I

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Q5➡ |
The disadvantage of write back strategy in cache is that.
i ➥ It requires local cache memory attached to every CPU in a multi processor environment.
ii ➥ Portions of main memory may be invalid.
iii ➥ It creates a write mechanism whenever there is a write operation to cache.
iv ➥ If generates repeated memory traffic.

Answer- II

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Q6➡ |
Cached and interleaved memories are ways of speeding up memory access between CPU’s and slower RAM. Which memory models are best suited (i.e. improves the performance most) for which programs ?
(i) Cached memory is best suited for small loops.
(ii) Interleaved memory is best suited for small loops
(iii) Interleaved memory is best suited for large sequential code.
(iv) Cached memory is best suited for large sequential code.
i ➥ (iv) and (iii) are true.
ii ➥ (i) and (ii) are true.
iii ➥ (iv) and (ii) are true.
iv ➥ (i) and (iii) are true.

Answer- IV

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Q7➡ |
Block or Buffer caches are used to
i ➥ speed up main memory Read operations
ii ➥ increase the capacity of main memory
iii ➥ handle interrupts
iv ➥ improve disk performance

Answer- I

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Q8➡ |
The performance of a file system depends upon the cache hit rate. If it takes 1 msec to satisfy a request from the cache but 10 msec to satisfy a request if a disk read is needed, then the mean time (ms) required for a hit rate ‘h’ is given by :
i ➥ h + 10 (1 – h)
ii ➥ (1 – h) + 10 h
iii ➥ 1
iv ➥ 10

Answer- I

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Q9➡ |
In _ method, the word is written to the block in both the cache and main memory, in parallel.
i ➥ Direct mapping
ii ➥ Write protected
iii ➥ Write back
iv ➥ Write through

Answer- IV

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Q10➡ |
Consider a system with 2 level cache. Access times of Level 1, Level 2 cache and main memory are 0.5 ns, 5 ns and 100 ns respectively. The hit rates of Level 1 and Level 2 caches are 0.7 and 0.8 respectively. What is the average access time of the system ignoring the search time within cache?
i ➥ 24.35 ns
ii ➥ 35.20 ns
iii ➥ 20.75 ns
iv ➥ 7.55 ns

Answer- IV

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Q11➡ |
A cache memory needs an access time of 30 ns and main memory 150 ns, what is the average access time of CPU (assume hit ratio = 80%)?
i ➥ 150
ii ➥ 80
iii ➥ 70
iv ➥ 60

Answer- IV

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Q12➡ |
Consider a system with 2 level cache. Access times of Level 1 cache, Level 2 cache and main memory are 1 ns, 10 ns, and 500 ns, respectively. The hit rates of Level 1 and Level 2 caches are 0.8 and 0.9, respectively. What is the average access time of the system ignoring the search time within the cache?
i ➥ 12.6
ii ➥ 12.4
iii ➥ 12.8
iv ➥ 13.0

Answer- I

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Q13➡ |
A dynamic RAM has a memory cycle time of 64 nsec. It has to be refreshed 100 times per msec and each refresh takes 100 nsec. What percentage of the memory cycle time is used for refreshing?
i ➥ 1
ii ➥ 10
iii ➥ 64
iv ➥ 6.4

Answer- I

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Memory hierarchy of COA| UGC NET|GATE

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