GATE/NET Digital Logic Design Practice Test Set6

Q1➡ |
The output of a sequential circuit depends on

i ➥ Present input only

ii ➥ Past input only

iii ➥ Both present and past input

iv ➥ None of the above

Q2➡ |
Which of the following flip-flops is free from race condition ?

i ➥ T flip-flop

ii ➥ SR flip-flop

iii ➥ Master-slave JK flip-flop

iv ➥ None of the above

Q3➡ |
A negative edge triggered flip flop transfers data from input on the:

i ➥ LOW to HIGH transition of clock pulse

ii ➥ BEFORE transition of clock pulse

iii ➥ HIGH to LOW transition of clock pulse

iv ➥ WITHOUT transition of clock pulse

Q4➡ |
The gates required to build a half adder are

i ➥ Ex-OR gate and NOR gate

ii ➥ Ex-OR gate and OR gate

iii ➥ Ex-OR gate and AND gate

iv ➥ Four NAND gates

Q5➡ |
In order to implement an n-variable switching function, a MUX must have

i ➥ 2ⁿ inputs

ii ➥ 2ⁿ + 1 inputs

iii ➥ 2^n-1 inputs

iv ➥ 2ⁿ – 1 inputs

Digital Logic Design

Set-1

Set-2

Set-3