GATE/NET Digital Logic Design Practice Test Set9

GATE/NET Digital Logic Design Practice Test Set9

Q16➡ |
If four 4 input multiplexers drive a 4 input multiplexer, we get a :
i ➥ 16 input MUX
ii ➥ 8 input MUX
iii ➥ 4 input MUX
iv ➥ 2 input MUX

Q17➡ |
The characteristic equation of a JK flip flop is :
i ➥ Qn+1 = J.Qn +K.Qn
ii ➥ Qn+1 = J.Q’n +K’Qn
iii ➥ Qn+1= QnJ.K
iv ➥ Qn+1= (J+K)Qn

Q18➡ |
Which of the following input combination is not desirable for SR flip flop ?
i ➥ S = 0, R = 0
ii ➥ S = 0, R = 1
iii ➥ S = 1, R = 0
iv ➥ S = 1, R = 1

Q19➡ |
A combinational logic circuit that is used when it is desired to send data from two more source through a single transmission line is known as______.
i ➥ Demultiplexer
ii ➥ Encoder
iii ➥ Decoder
iv ➥ Multiplexer

Q20➡ |
A/an ________, also called a dta selector, is a combinational circuit with more than on input line, one output line and more than one selection line.
i ➥ De multiplexer
ii ➥ Multiplexer or MUX
iii ➥ Operational amplifier
iv ➥ Integrated circuit

Test Date 16-01-2022

Digital Logic Design

Set-1 Set-2 Set-3 Set-4 Set-5

Test Date 09-01-2022

Digital Logic Design

Set-1 Set-2 Set-3 Set-4 Set-5


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